Bump yosys-plugins from c87f7b0
to d849fd4
#591
Merged
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Bumps yosys-plugins from
c87f7b0
tod849fd4
.Commits
d849fd4
Merge pull request #272 from antmicro/verilog-via-uhdm-force-parsefb94f80
Merge pull request #270 from antmicro/read_systemverilog_alias47c71ac
Force -parse flag for Surelog when reading Verilog directly3494b2b
Add 'read_systemverilog' command5c7d58a
Merge pull request #269 from tpagarani/adder_mapaf9d4b2
update adder techmap to implement last 2 bits into regular logicDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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