Force -parse flag for Surelog when reading Verilog directly

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
chipsalliance · Mar 16, 2022 · 47c71ac · 47c71ac
1 parent 5c7d58a
commit 47c71ac
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/uhdm-plugin/uhdmsurelogastfrontend.cc b/uhdm-plugin/uhdmsurelogastfrontend.cc
@@ -110,6 +110,12 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
         if (!success) {
             log_error("Error parsing Surelog arguments!\n");
         }
+        // Force -parse flag settings even if it wasn't specified
+        clp->setwritePpOutput(true);
+        clp->setParse(true);
+        clp->setCompile(true);
+        clp->setElaborate(true);
+
         SURELOG::scompiler *compiler = nullptr;
         const std::vector<vpiHandle> uhdm_design = executeCompilation(symbolTable, errors, clp, compiler);