lnis-uofu · tangxifan · Oct 31, 2021 · Oct 29, 2021 · Oct 29, 2021 · Oct 29, 2021
diff --git a/.gitmodules b/.gitmodules
@@ -1,4 +1,4 @@
 [submodule "yosys"]
 	path = yosys
-	url = https://github.com/QuickLogic-Corp/yosys.git
-	branch = quicklogic-rebased
+	url = https://github.com/YosysHQ/yosys
+    branch = release-branch-0.10
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -143,6 +143,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                                   const std::string& circuit_name,
                                                   const AtomContext& atom_ctx,
                                                   const VprNetlistAnnotation& netlist_annotation,
+                                                  const PinConstraints& pin_constraints,
                                                   const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -157,7 +158,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                              std::vector<std::string>(),
                                              std::string(FPGA_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
-                                             PinConstraints(),
+                                             pin_constraints,
                                              explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@@ -301,6 +302,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   /* Call defined top-level module */
   print_verilog_random_testbench_fpga_instance(fp, circuit_name,
                                                atom_ctx, netlist_annotation,
+                                               pin_constraints,
                                                options.explicit_port_mapping());
 
   /* Call defined benchmark */

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
@@ -83,7 +83,7 @@ opt_expr -mux_undef
 simplemap
 opt_expr
 opt_merge
-opt_rmdff
+opt_dff
 opt_clean
 opt
 

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
@@ -25,12 +25,12 @@ opt_clean
 # demote inout ports to input or output port
 # with follow-up optimizations to clean up AST
 deminout
-opt
+opt -nodffe -nosdff
 
 opt_expr
 opt_clean
 check
-opt
+opt -nodffe -nosdff
 wreduce -keepdc
 peepopt
 pmuxtree
@@ -58,10 +58,10 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions
 techmap
 alumacc
 share
-opt
+opt -nodffe -nosdff
 fsm
 # Run a quick follow-up optimization to sweep out unused nets/signals
-opt -fast
+opt -fast -nodffe -nosdff
 # Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
 memory -nomap
 opt_clean
@@ -78,14 +78,15 @@ opt -undriven -fine
 #########################
 # Map flip-flops
 #########################
+dfflegalize -cell $_DFF_P_ 0
 techmap -map +/adff2dff.v
 opt_expr -mux_undef
 simplemap
 opt_expr
 opt_merge
-opt_rmdff
+opt_dff -nodffe -nosdff
 opt_clean
-opt
+opt -nodffe -nosdff
 
 #########################
 # Map LUTs

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
@@ -67,7 +67,7 @@ opt_expr -mux_undef
 simplemap
 opt_expr
 opt_merge
-opt_rmdff
+opt_dff
 opt_clean
 opt
 

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
@@ -74,7 +74,7 @@ opt_expr -mux_undef
 simplemap
 opt_expr
 opt_merge
-opt_rmdff
+opt_dff
 opt_clean
 opt
 
@@ -93,4 +93,4 @@ stat
 # Output netlists
 #########################
 opt_clean -purge
-write_blif ${OUTPUT_BLIF}
+write_blif ${OUTPUT_BLIF}
diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -260,7 +260,7 @@ module MULTI_MODE_DFFSRQ (
 );
 
 wire post_set = mode[1] ? ~SET : SET;
-wire post_reset = mode[0] ? ~RST : RST;
+wire post_rst = mode[0] ? ~RST : RST;
 
 DFFSRQ FF_CORE (.SET(post_set),
                 .RST(post_rst),
@@ -284,7 +284,7 @@ module MULTI_MODE_DFFRQ (
   input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
 );
 
-wire post_reset = mode ? ~RST : RST;
+wire post_rst = mode ? ~RST : RST;
 
 DFFRQ FF_CORE (.RST(post_rst),
                .CK(CK),

diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh
@@ -8,12 +8,14 @@ PYTHON_EXEC=python3.8
 ##############################################
 echo -e "QuickLogic regression tests";
 
-echo -e "Testing yosys flow using custom ys script for running quicklogic device";
-run-task quicklogic_tests/flow_test --debug --show_thread_logs
+# TODO: Disabled all the tests here because Quicklogic's synthesis script is not in Yosys v0.10 release. Will bring back once Quicklogic manages to merge their contribution to Yosys upstream
 
-echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
-run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
-run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
-
-echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
-run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs
+##echo -e "Testing yosys flow using custom ys script for running quicklogic device";
+##run-task quicklogic_tests/flow_test --debug --show_thread_logs
+##
+##echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
+##run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
+##run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
+##
+##echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
+##run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs
diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 # Runtime of this bitstream generation should not exceed 3 minutes as a QoR requirement
@@ -19,7 +19,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_route_chan_width=50
 openfpga_vpr_device_layout=48x48
 

diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 # Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement
@@ -19,7 +19,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_route_chan_width=100
 openfpga_vpr_device_layout=96x96
 

diff --git a/yosys b/yosys