Use Yosys HQ v0.10 as a submodule

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue: Yosys plugin support #371
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• Current Yosys submodule is a QuickLogic version. As agreed in Yosys plugin support #371 , we should go for the yosys HQ version where we have most developers and updates

What does this pull request change?

This PR improves in the following aspects:

• Switch Yosys submodule to Yosys HQ v0.10 release; Quicklogic submodule is removed
• Update yosys script by replacing the deprecated command opt_rmdff with opt_dff
• Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected (reported in Yosys plugin support #371 )

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

• submodules

Impact of the pull request

• Require a change on Quality of Results (QoR)

The yosys v0.10 changes the number of BRAMs for some VTR benchmarks.

 INFO (     MainThread) - Task execution completed
ERROR: Benchmark 00_memset_MIN_ROUTE_CHAN_WIDTH failed in checking 'memory_blocks'
Found: 0 but expected: 1 outside range [20.0%, 10000.0%]
ERROR: Benchmark 00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH failed in checking 'memory_blocks'
Found: 0 but expected: 1 outside range [20.0%, 10000.0%]
INFO: Checked 26 metrics
INFO: See 2 QoR failures

• Break back-compatibility. If so, please list who may be influenced.

All the yosys scripts have been updated. If any tape-out has used the yosys scripts, they require a change.

[tangxifan]

@tpagarani @coolbreeze413 Please be aware of this

[tangxifan]

@tpagarani @ganeshgore @coolbreeze413 This PR is ready to go now.