[DO NOT MERGE] Dummy test PR to check auto-linting (syntax check)

.github/workflows/verible-auto-lint.yml

@@ -13,7 +13,6 @@ jobs:
         exclude_paths: |
           ./doc
         extra_args: "--check_syntax=true"
-        verible_version: "v0.0-3100-gd75b1c47"
         extensions: |
           .sv
           .v

design/rtl/alu_to_fail.sv

@@ -0,0 +1,60 @@
+`default_nettype none
+`timescale 1ns/1ns
+
+// ARITHMETIC-LOGIC UNIT
+// > Executes computations on register values
+// > In this minimal implementation, the ALU supports the 4 basic arithmetic operations
+// > Each thread in each core has it's own ALU
+// > ADD, SUB, MUL, DIV instructions are all executed here
+module alu (
+    input wire clk
+    input wire reset,
+    input wire enable, // If current block has less threads then block size, some ALUs will be inactive
+
+    input reg [2:0] core_state,
+
+    input reg [1:0] decoded_alu_arithmetic_mux,
+    input reg decoded_alu_output_mux,
+
+    input reg [7:0] rs,
+    input reg [7:0] rt,
+    output wire [7:0] alu_out
+;
+    localparam ADD = 2'b00,
+        SUB = 2'b01,
+        MUL = 2'b10,
+        DIV = 2'b11;
+
+    reg [7:0] alu_out_reg;
+    assign alu_out = alu_out_reg;
+
+    always @(posedge clk) begin 
+        if (reset) begin 
+            alu_out_reg <= 8'b0;
+        end else if (enable) begin
+            // Calculate alu_out when core_state = EXECUTE
+            if (core_state == 3'b101) begin 
+                if (decoded_alu_output_mux == 1) begin 
+                    // Set values to compare with NZP register in alu_out[2:0]
+                    alu_out_reg <= {5'b0, (rs - rt > 0), (rs - rt == 0), (rs - rt < 0)};
+                end else begin 
+                    // Execute the specified arithmetic instruction
+                    case (decoded_alu_arithmetic_mux)
+                        ADD: begin 
+                            alu_out_reg <= rs + rt;
+                        end
+                        SUB:  
+                            alu_out_reg <= rs - rt;
+                        end
+                        MUL: begin 
+                            alu_out_reg <= rs * rt;
+                        end
+                        DIV: begin 
+                            alu_out_reg <= rs / rt;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+endmodule