Skip to content

Releases: xobs/wishbone-utils

Risc-V Stability Across Reboots

06 Sep 08:40
Compare
Choose a tag to compare

With this version, the Risc-V controller is now able to keep working even across reflashing the FPGA. This has proven very useful for developing a new USB stack.

Raspberry Pi SPI Mode

31 Aug 12:47
Compare
Choose a tag to compare

v0.3.0 adds SPI support for arm, armv7, and aarch64 builds.

If you have a Fomu EVT, you can use 2-, 3-, or 4-wire SPI support to enable debugging the USB stack.

Other platforms do not yet have SPI support, but pull requests are welcome to add more!

MMU debug support

16 Aug 13:02
Compare
Choose a tag to compare
travis: re-enable other platforms

Signed-off-by: Sean Cross <sean@xobs.io>

Proper Serial support

26 Jul 11:20
Compare
Choose a tag to compare

This release adds Serial support! Use --serial [/path/to/serial/port] in order to access a Wishbone bus exposed via serial.

Works on all release platforms, including Windows.

v0.2.6: uart: add a first cut of a uart bridge

26 Jul 10:30
Compare
Choose a tag to compare
Allow users to specify --uart, in order to communicate with a target
device over a serial connection.

Signed-off-by: Sean Cross <sean@xobs.io>

v0.2.5: gdb: improve reliability and error messages during disconnects

25 Jul 09:24
Compare
Choose a tag to compare
If the device goes away (for example, during a reboot), reconnect to it.

The gdb client shouldn't need to care that this has happened, but it'd
be a good idea to print out messages on the console.

Signed-off-by: Sean Cross <sean@xobs.io>

v0.2.4: gdb: add empty response to "qTStatus" packet

25 Jul 04:17
Compare
Choose a tag to compare
We don't support trace status, but at least acknowledge it exists.

Signed-off-by: Sean Cross <sean@xobs.io>

v0.2.3: riscv: fix hardware breakpoints -- sync pc through threads

24 Jul 07:11
Compare
Choose a tag to compare
Now that we are properly synchronizing PC across threads, hardware
breakpoints now function correctly.

Signed-off-by: Sean Cross <sean@xobs.io>

v0.2.2: riscv: add cache flushing and pc-saving

23 Jul 12:50
Compare
Choose a tag to compare
Flush the cache as necessary.

Also, when we hit a breakpoint, save the program counter so we can
restore it later.

Signed-off-by: Sean Cross <sean@xobs.io>

v0.2.1: random-test: add option to limit number of random loops

20 Jul 07:21
Compare
Choose a tag to compare
For reliability tests, add a parameter to limit the maximum number of
successful loops to run through before we exit.

Signed-off-by: Sean Cross <sean@xobs.io>