riscv: handle NoException exceptions

Signed-off-by: Sean Cross <sean@xobs.io>
xobs · Sep 6, 2019 · f19e9d6 · f19e9d6
1 parent 3e900d3
commit f19e9d6
Showing 1 changed file with 8 additions and 8 deletions.
diff --git a/wishbone-tool/src/riscv/mod.rs b/wishbone-tool/src/riscv/mod.rs
@@ -715,11 +715,11 @@ impl RiscvCpu {
         self.controller.perform_resume(bridge, false)?;
 
         if let Some(exception) = self.last_exception.lock().unwrap().take() {
-            Ok(Some(format!("{}", exception)))
-        }
-        else {
-            Ok(None)
+            if exception != RiscvException::NoException {
+                return Ok(Some(format!("{}", exception)));
+            }
         }
+        Ok(None)
     }
 
     /// Step the CPU forward by one instruction.
@@ -728,11 +728,11 @@ impl RiscvCpu {
         self.controller.perform_resume(bridge, true)?;
 
         if let Some(exception) = self.last_exception.lock().unwrap().take() {
-            Ok(Some(format!("{}", exception)))
-        }
-        else {
-            Ok(None)
+            if exception != RiscvException::NoException {
+                return Ok(Some(format!("{}", exception)));
+            }
         }
+        Ok(None)
     }
 
     /// Convert a GDB `regnum` into a `RiscvRegister`