rtl: processor_templates: enable Zicntr ISA extension on minimal temp…

…lates (#1196)
stnolting · Mar 4, 2025 · 8ab1fec · 8ab1fec
2 parents 5753b32 + 24ff7c6
commit 8ab1fec
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diff --git a/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd b/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd
@@ -51,6 +51,8 @@ begin
     CLOCK_FREQUENCY              => CLOCK_FREQUENCY,   -- clock frequency of clk_i in Hz
     -- Boot Configuration --
     BOOT_MODE_SELECT             => 2,                 -- boot from pre-initialized interal IMEM
+    -- RISC-V CPU Extensions --
+    RISCV_ISA_Zicntr  => true,                         -- implement base counters?
     -- Internal Instruction memory --
     MEM_INT_IMEM_EN              => MEM_INT_IMEM_EN,   -- implement processor-internal instruction memory
     MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes

diff --git a/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd b/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
@@ -57,6 +57,8 @@ begin
     CLOCK_FREQUENCY   => CLOCK_FREQUENCY,   -- clock frequency of clk_i in Hz
     -- Boot Configuration --
     BOOT_MODE_SELECT  => 0,                 -- boot via internal bootloader
+    -- RISC-V CPU Extensions --
+    RISCV_ISA_Zicntr  => true,              -- implement base counters?
     -- Internal Instruction memory --
     MEM_INT_IMEM_EN   => MEM_INT_IMEM_EN,   -- implement processor-internal instruction memory
     MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes