[top] fix reset output descriptions

stnolting · Mar 4, 2025 · 5753b32 · 5753b32
1 parent df230ee
commit 5753b32
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -85,8 +85,8 @@ to all inputs and output so the synthesis tool can insert an explicit IO (bounda
 5+^| **Global Control (<<_processor_clocking>> and <<_processor_reset>>)**
 | `clk_i`          |  1 |  in | none  | global clock line, all registers triggering on rising edge
 | `rstn_i`         |  1 |  in | none  | global reset, asynchronous, **low-active**
-| `rstn_ocd_o`     |  1 | out | none  | <<_watchdog_timer_wdt>> reset output, synchronous, **low-active**
-| `rstn_wdt_o`     |  1 | out | none  | <<_on_chip_debugger_ocd>> reset output, synchronous, **low-active**
+| `rstn_ocd_o`     |  1 | out | none  | <<_on_chip_debugger_ocd>> reset output, synchronous, **low-active**
+| `rstn_wdt_o`     |  1 | out | none  | <<_watchdog_timer_wdt>> reset output, synchronous, **low-active**
 5+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
 | `jtag_tck_i`     |  1 |  in | `'L'` | serial clock
 | `jtag_tdi_i`     |  1 |  in | `'L'` | serial data input

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -143,8 +143,8 @@ entity neorv32_top is
     -- Global control --
     clk_i          : in  std_ulogic;                                        -- global clock, rising edge
     rstn_i         : in  std_ulogic;                                        -- global reset, low-active, async
-    rstn_ocd_o     : out std_ulogic;                                        -- watchdog reset output, low-active, sync
-    rstn_wdt_o     : out std_ulogic;                                        -- on-chip debugger reset output, low-active, sync
+    rstn_ocd_o     : out std_ulogic;                                        -- on-chip debugger reset output, low-active, sync
+    rstn_wdt_o     : out std_ulogic;                                        -- watchdog reset output, low-active, sync
 
     -- JTAG on-chip debugger interface (available if OCD_EN = true) --
     jtag_tck_i     : in  std_ulogic := 'L';                                 -- serial clock

diff --git a/rtl/system_integration/neorv32_vivado_ip.vhd b/rtl/system_integration/neorv32_vivado_ip.vhd
@@ -136,8 +136,8 @@ entity neorv32_vivado_ip is
     -- ------------------------------------------------------------
     clk            : in  std_logic;
     resetn         : in  std_logic; -- low-active
-    ocd_resetn     : out std_logic; -- watchdog reset output, low-active, sync
-    wdt_resetn     : out std_logic; -- on-chip debugger reset output, low-active, sync
+    ocd_resetn     : out std_logic; -- on-chip debugger reset output, low-active, sync
+    wdt_resetn     : out std_logic; -- watchdog reset output, low-active, sync
     -- ------------------------------------------------------------
     -- AXI4-Lite Host Interface (available if XBUS_EN = true)
     -- ------------------------------------------------------------