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Topology Processor: Components with single bus are ignored #2309

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jeandemanged opened this issue Oct 2, 2022 · 0 comments · Fixed by #2310
Closed

Topology Processor: Components with single bus are ignored #2309

jeandemanged opened this issue Oct 2, 2022 · 0 comments · Fixed by #2310

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@jeandemanged
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jeandemanged commented Oct 2, 2022

  • Do you want to request a feature or report a bug?
    that is debatable

  • What is the current behavior?
    Islands (components) with a single bus are ignored.
    Precision: This happens only for BUS-BREAKER topology style. In NODE-BREAKER a single busbar e.g. with a load and a generator and no branch connected is correctly reported as a synchronous component.

  • If the current behavior is a bug, please provide the steps to reproduce and if possible a minimal demo of the problem
    PR reproducing the issue: Topology Processor: Components with single bus are ignored (#2309) #2310

  • What is the expected behavior?
    Islands (components) with a single bus to be reported just like any island.

  • What is the motivation / use case for changing the behavior?
    Current behavior is confusing. A single bus network should be valid and could even be computed in LoadFlow (single V-theta bus).

jeandemanged added a commit that referenced this issue Oct 2, 2022
Signed-off-by: Damien Jeandemange <damien.jeandemange@artelys.com>
@jeandemanged jeandemanged linked a pull request Oct 3, 2022 that will close this issue
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miovd pushed a commit that referenced this issue Oct 5, 2022
…2310)

Signed-off-by: Damien Jeandemange <damien.jeandemange@artelys.com>
Co-authored-by: Anne Tilloy <anne.tilloy@rte-france.com>
Co-authored-by: Luma <zamarrenolm@aia.es>
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