[ci] No module named 'google_verible_verilog_syntax_py' #7440
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The "no module named google_..." error is a problem in the prim setup, but we have a fall-back in place, so it shouldn't cause any build to fail. (I'll have a fix in the coming days.) Thanks for filing an issue for it! The bitstream error is missing a bit of context (and it's certainly not connected to the verible syntax issue), so let's maybe handle that in a separate issue? |
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The include path to a Python module we depend on was dependent on the working directory, leading to errors like No module named 'google_verible_verilog_syntax_py' when running primgen, and prevented the Verible parser from actually being used. Fixes lowRISC#7440 Signed-off-by: Philipp Wagner <phw@lowrisc.org>
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I found this warning while analyzing the failure of building FPGA bitstream.
BTW, looks like the FPGA build fails even the bitstream is generated.
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