[ci] No module named 'google_verible_verilog_syntax_py' (2024)

[lmg260a]

Description

I am encountering this problem when getting the toolchain running on CentOS. This issue was marked closed in 2021.

[rswarbrick]

Sorry, but you're going to have to give us a little bit more information before we can help. When you say an issue was closed, do you mean #7440?

Can you give me the command you're trying to run? Are you just noticing the "Verible parser failed" message from primgen.py? If so, I don't think there's a problem: the regex fallback that it uses should work just fine.

If there's something else going on, please can you give some more information and re-open?

[lmg260a]

I've learned to "stay within the lines" or else I have problems downstream. That means getting the exact same results as the developers.
So what do I need to change to get the google_verible_verilog_syntax_py to be picked up? I've been grepping the opentitan repo and reading the opentitan docs and using Google on the internet, and I can't spot what I'm doing wrong.

[rswarbrick]

That makes sense, but I'm not sure this library in particular really matters :-) It's not installed on my machine either and the regex fallback seems to work fine. If there's something that's not working, let us know what you're trying to do (and what you'd expect to happen). We can definitely try to help!

[lmg260a]

OK, well where I'm stuck is I run this line in https://opentitan.org/book/doc/getting_started/build_sw.html.
To install the correct version of bazel, build, and run a single test with Verilator, run:
$REPO_TOP/bazelisk.sh test --test_output=streamed --disk_cache=~/bazel_cache //sw/device/tests:uart_smoketest_sim_verilator

This reports:
[2024-03-27T04:27:30Z INFO opentitantool::command::console] ExitSuccess("PASS!\r\n")
[2024-03-27T04:27:30Z INFO opentitantool] Command result: success.
[2024-03-27T04:27:30Z INFO opentitantool] Command result: success.
//sw/device/tests:uart_smoketest_sim_verilator PASSED in 101.0s

Executed 1 out of 1 test: 1 test passes.

But it's not obvious (to me) what the next steps are. My goal is to run chip-level sim with UVM.
So I tried doing
bazelisk.sh build //sw/device/lib/testing/test_rom:test_rom

Which was listed in the docs as building the test-ROM.
But I get zero output at all - it just dies.

So I tried ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx
which is also in the docs, and I get:

INFO: [dvsim] [proj_root]: /opentitan/U2/opentitan
INFO: [SimCfg] [scratch_path]: [chip] [/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs]
ERROR: [Modes] Test "chip_plic_all_irqs" added to regression "xcelium_ci_0" not found!
ERROR: [Modes] Test "chip_sw_aes_prng_reseed" added to regression "V2" not found!
ERROR: [Modes] Test "chip_plic_all_irqs" added to regression "V2" not found!
ERROR: [Modes] Test "chip_sw_aes_force_prng_reseed" added to regression "V2" not found!
INFO: [StatusPrinter] ESC[1m ESC[0m [ legend ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]
INFO: [StatusPrinter] ESC[1m00:00:00 ESC[0m [ build ]: [Q: 0, D: 1, P: 0, F: 0, K: 0, T: 1] 0% chip:default
WARNING: [Deploy] chip:default: Job runtime not found in the log. Using dvsim-maintained job_runtime instead.
ERROR: [Scheduler] [00:00:01]: [build]: [status] [chip:default: F]
INFO: [StatusPrinter] ESC[1m00:00:01 ESC[0m [ build ]: [Q: 0, D: 0, P: 0, F: 1, K: 0, T: 1] 100%
INFO: [StatusPrinter] ESC[1m00:00:01 ESC[0m [ run ]: [Q: 0, D: 0, P: 0, F: 0, K: 5, T: 5] 100%
INFO: [FlowCfg] [results]: [chip]:

CHIP Simulation Results

So I'm guessing that I'm missing a step or something. The docs are great for getting the first Verilator test to run, but abstract after that - they just list possibilities and grammars. So I've no idea what to do, or how to debug.

[rswarbrick]

Hmm. The dvsim.py command using chip_sim_cfg.hjson looks sensible to me. It looks like building the test itself failed for some reason. I think you'll have to look in your local scratch directory. There should probably be a build.log, which might give more of a hint about what went wrong.

Running locally (in a branch called "tmp"), I ended up with a log file at scratch/tmp/chip_earlgrey_asic-sim-vcs/default/build.log.

[lmg260a]

It says "fusesoc" not found. When I searched for "fusesoc*", I got a couple of hits but nothing appropriate. I've re-read the onlin docs and don't spot where I need to install fusesoc. Any suggestions? (I really appreciate all the help, BTW!)

[lmg260a]

Here's the complete build.log in case it helps.

make -f /opentitan/U2/opentitan/hw/dv/tools/dvsim/sim.mk build build_cmd=vcs build_dir=/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default build_opts='+define+TOP_LEVEL_DV +define+UVM +define+UVM_NO_DEPRECATED +define+UVM_REGEX_NO_DPI +define+UVM_REG_ADDR_WIDTH=32 +define+UVM_REG_DATA_WIDTH=64 +define+UVM_REG_BYTENABLE_WIDTH=8 +define+SIMULATION +define+DUT_HIER=tb.dut -sverilog -full64 -licqueue -ntb_opts uvm-1.2 -timescale=1ns/1ps -Mdir=/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv.csrc -o /opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv -f /opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/sim-vcs/lowrisc_dv_chip_sim_0.1.scr -lca -top clkmgr_bind -top pwrmgr_bind -top rstmgr_bind -top sec_cm_prim_onehot_check_bind -top sec_cm_prim_sparse_fsm_flop_bind -top top_earlgrey_error_injection_ifs_bind -top top_earlgrey_bind -top xbar_main_bind -top xbar_peri_bind -top tb +incdir+/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default +warn=SV-NFIVC +warn=noUII-L +warn=noLCA_FEATURES_ENABLED +warn=noBNA -assert svaext -xlrm uniq_prior_final -CFLAGS --std=c99 -CFLAGS -fno-extended-identifiers -CFLAGS --std=c++11 -LDFLAGS -Wl,--no-as-needed -debug_region=cell+lib -debug_access+f +define+VCS -error=IPDW -error=UPF_ISPND -error=IGPA -error=PCSRMIO -error=AOUP -error=ELW_UNBOUND -error=IUWI -error=INAV -error=SV-ISC -error=OSVF-NPVIUFPI -error=DPIMI -error=IPDASP -error=CM-HIER-FNF -error=CWUC -error=MATN -error=STASKW_NDTAZ1 -error=TMPO -error=SV-OHCM -error=ENUMASSIGN -error=TEIF -deraceclockdata -assert novpi+dbgopt -xprop=/opentitan/U2/opentitan/hw/top_earlgrey/dv/vcs_xprop.cfg -xprop=mmsopt -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_otbn_memutil_0 -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_ip_otbn_tracer_0/cpp -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_verilator_memutil_dpi_0/cpp -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_verilator_memutil_dpi_scrambled_0/cpp -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_secded_enc_0 -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_scramble_model_0 -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_crypto_prince_ref_0.1 -lelf -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_model_aes_1.0 -lcrypto -CFLAGS -I/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/src/lowrisc_dv_dpi_tcp_server_0.1 -lutil' post_build_cmds='' pre_build_cmds='' proj_root=/opentitan/U2/opentitan sv_flist_gen_cmd=fusesoc sv_flist_gen_dir=/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default/sim-vcs sv_flist_gen_opts='--cores-root /opentitan/U2/opentitan run --flag=fileset_top --target=sim --build-root=/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default --setup lowrisc:dv:chip_sim:0.1'

make[1]: Entering directory '/opentitan/U2/opentitan'
[make]: pre_build
mkdir -p /opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default
[make]: gen_sv_flist
cd /opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default && fusesoc --cores-root /opentitan/U2/opentitan run --flag=fileset_top --target=sim --build-root=/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/default --setup lowrisc:dv:chip_sim:0.1
/bin/bash: line 1: fusesoc: command not found
make[1]: *** [/opentitan/U2/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 127
make[1]: Leaving directory '/opentitan/U2/opentitan'

[lmg260a]

I discovered by searching the internet that I needed to put ~/.local/bin on my search path. So I reran and it died when it couldn't find VCS. I don't have a VCS license, so where do I find the files that are going to be fed into VCS, so I can copy them and make them run in Questasim?

[lmg260a]

The build.log reported that vcs wasn't found.
stderr reported:
INFO: [dvsim] [proj_root]: /opentitan/U2/opentitan
INFO: [SimCfg] [scratch_path]: [chip] [/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs]
ERROR: [Modes] Test "chip_plic_all_irqs" added to regression "xcelium_ci_0" not found!
ERROR: [Modes] Test "chip_sw_aes_force_prng_reseed" added to regression "V2" not found!
ERROR: [Modes] Test "chip_sw_aes_prng_reseed" added to regression "V2" not found!
ERROR: [Modes] Test "chip_plic_all_irqs" added to regression "V2" not found!
INFO: [StatusPrinter] �[1m �[0m [ legend ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]

[lmg260a]

When I did the same command, but --tool=questa, I got this on stdout; I didn't spot a logfile anywhere.

# INFO: [dvsim] [proj_root]: /opentitan/U2/opentitan
# INFO: [SimCfg] [scratch_path]: [chip] [/opentitan/U2/opentitan/scratch/master/chip_earlgrey_asic-sim-questa]
# ERROR: [SimCfg] Mode "questa_otbn_memutil_build_opts" enabled on the command line is not defined

When I did the same command but --tool verilator I got:

INFO: [dvsim] [proj_root]: /opentitan/U2/opentitan
ERROR: [CfgFactory] '/opentitan/U2/opentitan/hw/dv/tools/dvsim/verilator.hjson': Value for key 'run_dir' is '{scratch_path}/{run_dir_name}/out', but we already had a conflicting value of '{scratch_path}/{run_dir_name}/latest'.

So only VCS option appears to get as far as generating commands for the simulator.
I was hoping that at least Verilator would work.

[rswarbrick]

Two things:

• For the "not defined" problem: this is because we haven't tried to run OTBN tests with Questa yet. If you add something to hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson, you should probably be able to get the build working.
• For Verilator: UVM (that we're using) isn't quite supported by Verilator yet. They're working on it, but we're not going to be able to run UVM testbenches with Verilator quite yet.

[lmg260a]

Thanks! I'm still figuring out things - is there an easy way to run all tests known to pass for a particular simulator, so I don't try to run things that are known not to work?

[lmg260a]

For example, this test has "verilator" in its name. But it does run, so how would I go find an equivalent test that I could run using Questa? bazelisk.sh doesn't have a "--tool" option like dvsim.py.

bazelisk.sh test --test_output=streamed --disk_cache=~/bazel_cache //sw/device/tests:uart_smoketest_sim_verilator

I know that Questa isn't officially supported, but I want to work to get Questa to run. My problem is, I need a good starting point of a tiny test that works in Verilator, so I can compare waveforms, logs, etc. So a uart smoketest would seem a good candidate.

After that - is there a tiny test that uses UVM?

[lmg260a]

In case it's of use to you, The smoketest_sim_verilator passes for me.
[692 / 693] Testing //sw/device/tests:uart_smoketest_sim_verilator; 95s local
INFO: Elapsed time: 1375.679s, Critical Path: 1365.97s
INFO: 151 processes: 41 internal, 2 local, 108 processwrapper-sandbox.
INFO: Build completed successfully, 151 total actions
//sw/device/tests:uart_smoketest_sim_verilator PASSED in 95.6s