Async Reset support for Atomics, FPU, and TLBroadcast

src/main/scala/diplomacy/LazyModule.scala

@@ -2,7 +2,8 @@
 
 package freechips.rocketchip.diplomacy
 
-import Chisel._
+import Chisel.{defaultCompileOptions => _, _}
+import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import chisel3.{RawModule, MultiIOModule, withClockAndReset}
 import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
 import freechips.rocketchip.config.Parameters

src/main/scala/tile/FPU.scala

@@ -3,7 +3,8 @@
 
 package freechips.rocketchip.tile
 
-import Chisel._
+import Chisel.{defaultCompileOptions => _, _}
+import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import Chisel.ImplicitConversions._
 
 import freechips.rocketchip.config.Parameters
@@ -392,7 +393,7 @@ trait HasFPUParameters {
   }
 }
 
-abstract class FPUModule(implicit p: Parameters) extends CoreModule()(p) with HasFPUParameters
+abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
 
 class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
   class Output extends Bundle {
@@ -411,7 +412,13 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime
   val in = RegEnable(io.in.bits, io.in.valid)
   val valid = Reg(next=io.in.valid)
 
-  val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
+  // NOTE-2361: the withReset(false.B) in this file
+  // is to enable AsyncReset in this module, while this
+  // submodule does not contain any sequential elements.
+  // See https://github.com/chipsalliance/rocket-chip/issues/2361
+  // This withReset(false.B) can be removed once the above issue is
+  // resolved.
+  val dcmp = withReset(false.B) {Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))}
   dcmp.io.a := in.in1
   dcmp.io.b := in.in2
   dcmp.io.signaling := !in.rm(1)
@@ -438,8 +445,8 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime
     when (!in.ren2) { // fcvt
       val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
       intType := cvtType
-
-      val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
+      // See  NOTE-2361 above
+      val conv = withReset(false.B){Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))}
       conv.io.in := in.in1
       conv.io.roundingMode := in.rm
       conv.io.signedOut := ~in.typ(0)
@@ -497,7 +504,8 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) w
     // could be improved for RVD/RVQ with a single variable-position rounding
     // unit, rather than N fixed-position ones
     val i2fResults = for (t <- floatTypes) yield {
-      val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
+      // See  NOTE-2361 above
+      val i2f = withReset(false.B){Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))}
       i2f.io.signedIn := ~in.bits.typ(0)
       i2f.io.in := intValue
       i2f.io.roundingMode := in.bits.rm
@@ -593,10 +601,13 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
 
     //------------------------------------------------------------------------
     //------------------------------------------------------------------------
+
+    // See  NOTE-2361 above
     val mulAddRecFNToRaw_preMul =
-        Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
+      withReset(false.B) {Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))}
+    // See  NOTE-2361 above
     val mulAddRecFNToRaw_postMul =
-        Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
+        withReset(false.B) {Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))}
 
     mulAddRecFNToRaw_preMul.io.op := io.op
     mulAddRecFNToRaw_preMul.io.a  := io.a
@@ -622,7 +633,9 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
 
     //------------------------------------------------------------------------
     //------------------------------------------------------------------------
-    val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
+
+    // See  NOTE-2361 above
+    val roundRawFNToRecFN = withReset(false.B){Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))}
 
     val round_regs = if(latency==2) 1 else 0
     roundRawFNToRecFN.io.invalidExc         := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
@@ -658,7 +671,8 @@ class FPUFMAPipe(val latency: Int, val t: FType)
     when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
   }
 
-  val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
+  // See  NOTE-2361 above
+  val fma = withReset(false.B){Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))}
   fma.io.validin := valid
   fma.io.op := in.fmaCmd
   fma.io.roundingMode := in.rm
@@ -901,7 +915,8 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
 
     for (t <- floatTypes) {
       val tag = !mem_ctrl.singleOut // TODO typeTag
-      val divSqrt = Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0))
+      // See  NOTE-2361 above
+      val divSqrt = withReset(false.B){Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0))}
       divSqrt.io.inValid := mem_reg_valid && tag === typeTag(t) && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
       divSqrt.io.sqrtOp := mem_ctrl.sqrt
       divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)

src/main/scala/tilelink/Atomics.scala

@@ -2,7 +2,8 @@
 
 package freechips.rocketchip.tilelink
 
-import Chisel._
+import Chisel.{defaultCompileOptions => _, _}
+import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 
 import TLMessages._
 import TLPermissions._

src/main/scala/tilelink/Broadcast.scala

@@ -2,7 +2,8 @@
 
 package freechips.rocketchip.tilelink
 
-import Chisel._
+import Chisel.{defaultCompileOptions => _, _}
+import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._

src/main/scala/util/CompileOptions.scala

@@ -0,0 +1,10 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.util
+
+import chisel3.ExplicitCompileOptions.NotStrict
+
+object CompileOptions {
+  /** Compatibility mode semantics except Module implicit reset should be inferred instead of Bool */
+  implicit val NotStrictInferReset = NotStrict.copy(inferModuleReset = true)
+}

wit-manifest.json

@@ -10,7 +10,7 @@
         "source": "git@github.com:sifive/api-chisel3-sifive.git"
     },
     {
-        "commit": "5ee1efa292394429e603dc878643aa1fed4ac020",
+        "commit": "7a343dce95a370f6cb7b9cf80e0694ac82dc94f8",
         "name": "chisel3",
         "source": "git@github.com:freechipsproject/chisel3.git"
     },