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Async Reset support for Atomics, FPU, and TLBroadcast #2362

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merged 9 commits into from
Mar 27, 2020
Merged

Async Reset support for Atomics, FPU, and TLBroadcast #2362

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53bac41
Bump chisel3 version on 3.2.x branch
mwachs5 Mar 25, 2020
c533db1
Convert FPU, Atomics, Broadcast to support async reset
mwachs5 Mar 24, 2020
00f7edf
Add a DefaultCompileOptions.NonStrictInferReset
jackkoenig Dec 6, 2019
e7de4aa
AsyncReset: revert change to LazyModule, will do in follow up PR
mwachs5 Mar 25, 2020
dc18813
FPU: MulAddRecFNPipe needs a reset
mwachs5 Mar 26, 2020
516bb01
FPU: DivSqrtRecFN_small also needs a reset
mwachs5 Mar 26, 2020
f91037e
Bump hardfloat for async reset support
mwachs5 Mar 26, 2020
00d0f96
FPU: revert workarounds for async reset support
mwachs5 Mar 26, 2020
aa63fd8
Merge remote-tracking branch 'origin/master' into fpu-atomics-broadca…
mwachs5 Mar 26, 2020
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2 changes: 1 addition & 1 deletion chisel3
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Submodule chisel3 updated from 5ee1ef to 7a343d
2 changes: 1 addition & 1 deletion hardfloat
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Submodule hardfloat updated 11 files
+1 −1 .gitignore
+43 −0 build.sbt
+1 −0 project/build.properties
+3 −3 src/main/scala/CompareRecFN.scala
+6 −6 src/main/scala/DivSqrtRecF64.scala
+6 −6 src/main/scala/DivSqrtRecF64_mulAddZ31.scala
+3 −3 src/main/scala/INToRecFN.scala
+9 −9 src/main/scala/MulAddRecFN.scala
+3 −3 src/main/scala/RecFNToIN.scala
+3 −3 src/main/scala/RecFNToRecFN.scala
+6 −6 src/main/scala/RoundAnyRawFNToRecFN.scala
14 changes: 7 additions & 7 deletions src/main/scala/tile/FPU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@

package freechips.rocketchip.tile

import Chisel._
import Chisel.{defaultCompileOptions => _, _}
import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
import Chisel.ImplicitConversions._

import freechips.rocketchip.config.Parameters
Expand Down Expand Up @@ -392,7 +393,7 @@ trait HasFPUParameters {
}
}

abstract class FPUModule(implicit p: Parameters) extends CoreModule()(p) with HasFPUParameters
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters

class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
Expand Down Expand Up @@ -438,7 +439,6 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType

val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
Expand Down Expand Up @@ -593,10 +593,9 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module

//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))

val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))

mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
Expand All @@ -622,6 +621,7 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module

//------------------------------------------------------------------------
//------------------------------------------------------------------------

val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))

val round_regs = if(latency==2) 1 else 0
Expand Down
3 changes: 2 additions & 1 deletion src/main/scala/tilelink/Atomics.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,8 @@

package freechips.rocketchip.tilelink

import Chisel._
import Chisel.{defaultCompileOptions => _, _}
import freechips.rocketchip.util.CompileOptions.NotStrictInferReset

import TLMessages._
import TLPermissions._
Expand Down
3 changes: 2 additions & 1 deletion src/main/scala/tilelink/Broadcast.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,8 @@

package freechips.rocketchip.tilelink

import Chisel._
import Chisel.{defaultCompileOptions => _, _}
import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
Expand Down
10 changes: 10 additions & 0 deletions src/main/scala/util/CompileOptions.scala
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Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
// See LICENSE.SiFive for license details.

package freechips.rocketchip.util

import chisel3.ExplicitCompileOptions.NotStrict

object CompileOptions {
/** Compatibility mode semantics except Module implicit reset should be inferred instead of Bool */
implicit val NotStrictInferReset = NotStrict.copy(inferModuleReset = true)
}
4 changes: 2 additions & 2 deletions wit-manifest.json
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[
{
"commit": "f36127349c5303e32dcc97ccdd3b491f51ec60e9",
"commit": "3f88b663c7324cf9a27f9e20b82382908bb4cc11",
"name": "hardfloat",
"source": "git@github.com:ucb-bar/berkeley-hardfloat.git"
},
Expand All @@ -10,7 +10,7 @@
"source": "git@github.com:sifive/api-chisel3-sifive.git"
},
{
"commit": "5ee1efa292394429e603dc878643aa1fed4ac020",
"commit": "7a343dce95a370f6cb7b9cf80e0694ac82dc94f8",
"name": "chisel3",
"source": "git@github.com:freechipsproject/chisel3.git"
},
Expand Down