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Syntax fixes; cleanup for clean compile; regenerated RDL; fixed port …
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…connections
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@calebofearth
calebofearth committed Nov 17, 2024
1 parent 6d80e1c commit f78dedb
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Showing 13 changed files with 213 additions and 209 deletions.
4 changes: 2 additions & 2 deletions src/integration/rtl/caliptra_reg.h
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Expand Up @@ -5518,8 +5518,8 @@
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (0x1000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (0xe000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (0x10000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (0x10000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (0x20000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
Expand Down
4 changes: 2 additions & 2 deletions src/integration/rtl/caliptra_reg_defines.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -5518,8 +5518,8 @@
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (32'h10000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
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8 changes: 4 additions & 4 deletions src/integration/rtl/caliptra_top.sv
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Expand Up @@ -97,10 +97,10 @@ module caliptra_top
input logic [63:0] strap_ss_uds_seed_base_addr,
input logic [31:0] strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset,
input logic [31:0] strap_ss_num_of_prod_debug_unlock_auth_pk_hashes,
input logic [63:0] strap_ss_strap_rsvd_0,
input logic [63:0] strap_ss_strap_rsvd_1,
input logic [63:0] strap_ss_strap_rsvd_2,
input logic [63:0] strap_ss_strap_rsvd_3,
input logic [31:0] strap_ss_strap_rsvd_0,
input logic [31:0] strap_ss_strap_rsvd_1,
input logic [31:0] strap_ss_strap_rsvd_2,
input logic [31:0] strap_ss_strap_rsvd_3,
input logic ss_debug_intent,

// Subsystem mode debug outputs
Expand Down
4 changes: 2 additions & 2 deletions src/soc_ifc/rtl/caliptra_top_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -107,8 +107,8 @@
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (0x1000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (0xe000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (0x10000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (0x10000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (0x20000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
Expand Down
4 changes: 2 additions & 2 deletions src/soc_ifc/rtl/caliptra_top_reg_defines.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -107,8 +107,8 @@
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (32'h10000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
Expand Down
2 changes: 1 addition & 1 deletion src/soc_ifc/rtl/soc_ifc_external_reg.rdl
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Original file line number Diff line number Diff line change
Expand Up @@ -124,7 +124,7 @@ reg {
rw_ro status[24]=0;
field {desc="DEV ID CSR ready"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} idevid_csr_ready[1]=0;
field {desc="Boot FSM State"; sw=r; hw=w ; /* no storage, no reset */} boot_fsm_ps[3];
field {desc="Indicates Caliptra is ready for Firmware Download"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_fw[1]=0;
field {desc="Indicates Caliptra is ready for Mailbox operations"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_mb_processing[1]=0;
field {desc="Indicates Caliptra is ready for RT flows"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_runtime[1]=0;
field {desc="Indicates Caliptra is ready for Fuses to be programmed.
Read-only to both Caliptra and SOC."; sw=r; hw=w ; /* no storage, no reset */} ready_for_fuses[1];
Expand Down
26 changes: 14 additions & 12 deletions src/soc_ifc/rtl/soc_ifc_reg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -468,7 +468,7 @@ module soc_ifc_reg (
struct packed{
logic next;
logic load_next;
} ready_for_fw;
} ready_for_mb_processing;
struct packed{
logic next;
logic load_next;
Expand Down Expand Up @@ -1522,7 +1522,7 @@ module soc_ifc_reg (
} idevid_csr_ready;
struct packed{
logic value;
} ready_for_fw;
} ready_for_mb_processing;
struct packed{
logic value;
} ready_for_runtime;
Expand Down Expand Up @@ -2623,27 +2623,27 @@ module soc_ifc_reg (
end
end
assign hwif_out.CPTRA_FLOW_STATUS.idevid_csr_ready.value = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value;
// Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_fw
// Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_mb_processing
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value;
next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value;
load_next_c = '0;
if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value & ~decoded_wr_biten[28:28]) | (decoded_wr_data[28:28] & decoded_wr_biten[28:28]);
next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value & ~decoded_wr_biten[28:28]) | (decoded_wr_data[28:28] & decoded_wr_biten[28:28]);
load_next_c = '1;
end
field_combo.CPTRA_FLOW_STATUS.ready_for_fw.next = next_c;
field_combo.CPTRA_FLOW_STATUS.ready_for_fw.load_next = load_next_c;
field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.next = next_c;
field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.load_next = load_next_c;
end
always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
if(~hwif_in.cptra_rst_b) begin
field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= 1'h0;
end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_fw.load_next) begin
field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_fw.next;
field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value <= 1'h0;
end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.load_next) begin
field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.next;
end
end
assign hwif_out.CPTRA_FLOW_STATUS.ready_for_fw.value = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value;
assign hwif_out.CPTRA_FLOW_STATUS.ready_for_mb_processing.value = field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value;
// Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_runtime
always_comb begin
automatic logic [0:0] next_c;
Expand Down Expand Up @@ -4442,6 +4442,7 @@ module soc_ifc_reg (
field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value <= field_combo.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.next;
end
end
assign hwif_out.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value = field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value;
end
for(genvar i0=0; i0<2; i0++) begin
// Field: soc_ifc_reg.SS_GENERIC_FW_EXEC_CTRL[].go
Expand All @@ -4464,6 +4465,7 @@ module soc_ifc_reg (
field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value <= field_combo.SS_GENERIC_FW_EXEC_CTRL[i0].go.next;
end
end
assign hwif_out.SS_GENERIC_FW_EXEC_CTRL[i0].go.value = field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value;
end
for(genvar i0=0; i0<8; i0++) begin
// Field: soc_ifc_reg.internal_obf_key[].key
Expand Down Expand Up @@ -6868,7 +6870,7 @@ module soc_ifc_reg (
assign readback_array[15][23:0] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.status.value : '0;
assign readback_array[15][24:24] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value : '0;
assign readback_array[15][27:25] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? hwif_in.CPTRA_FLOW_STATUS.boot_fsm_ps.next : '0;
assign readback_array[15][28:28] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value : '0;
assign readback_array[15][28:28] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value : '0;
assign readback_array[15][29:29] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value : '0;
assign readback_array[15][30:30] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? hwif_in.CPTRA_FLOW_STATUS.ready_for_fuses.next : '0;
assign readback_array[15][31:31] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value : '0;
Expand Down
134 changes: 62 additions & 72 deletions src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -201,7 +201,7 @@
input bit [24-1:0] status,
input bit [1-1:0] idevid_csr_ready,
input bit [3-1:0] boot_fsm_ps,
input bit [1-1:0] ready_for_fw,
input bit [1-1:0] ready_for_mb_processing,
input bit [1-1:0] ready_for_runtime,
input bit [1-1:0] ready_for_fuses,
input bit [1-1:0] mailbox_flow_done
Expand All @@ -210,7 +210,7 @@
status_cp : coverpoint status;
idevid_csr_ready_cp : coverpoint idevid_csr_ready;
boot_fsm_ps_cp : coverpoint boot_fsm_ps;
ready_for_fw_cp : coverpoint ready_for_fw;
ready_for_mb_processing_cp : coverpoint ready_for_mb_processing;
ready_for_runtime_cp : coverpoint ready_for_runtime;
ready_for_fuses_cp : coverpoint ready_for_fuses;
mailbox_flow_done_cp : coverpoint mailbox_flow_done;
Expand Down Expand Up @@ -633,17 +633,13 @@
endgroup
covergroup soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg with function sample(
input bit [1-1:0] iTRNG_en,
input bit [1-1:0] QSPI_en,
input bit [1-1:0] I3C_en,
input bit [1-1:0] UART_en,
input bit [3-1:0] RSVD_en,
input bit [1-1:0] LMS_acc_en,
input bit [1-1:0] ACTIVE_MODE_en
);
option.per_instance = 1;
iTRNG_en_cp : coverpoint iTRNG_en;
QSPI_en_cp : coverpoint QSPI_en;
I3C_en_cp : coverpoint I3C_en;
UART_en_cp : coverpoint UART_en;
RSVD_en_cp : coverpoint RSVD_en;
LMS_acc_en_cp : coverpoint LMS_acc_en;
ACTIVE_MODE_en_cp : coverpoint ACTIVE_MODE_en;

Expand Down Expand Up @@ -961,8 +957,8 @@

endgroup

/*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_bit_cg with function sample(input bit reg_bit);
/*----------------------- SOC_IFC_REG__CPTRA_CAP_LOCK COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_CAP_LOCK_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
Expand All @@ -973,42 +969,16 @@
}

endgroup
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_fld_cg with function sample(
input bit [32-1:0] hash
);
option.per_instance = 1;
hash_cp : coverpoint hash {
bins zero_val = {32'h0};
bins rand_val[64] = {[1:32'hFFFF_FFFE]};
bins ones_val = {{32{1'b1}}};
wildcard bins set = (0 => 32'h????_????);
wildcard bins clr = (32'h????_???? => 0);
}

endgroup

/*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH_LOCK COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
}
reg_bit_edge_cp : coverpoint reg_bit {
bins rise = (0 => 1);
bins fall = (1 => 0);
}

endgroup
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_fld_cg with function sample(
covergroup soc_ifc_reg__CPTRA_CAP_LOCK_fld_cg with function sample(
input bit [1-1:0] lock
);
option.per_instance = 1;
lock_cp : coverpoint lock;

endgroup

/*----------------------- SOC_IFC_REG__CPTRA_DEBUG_AUTH_PK_HASH_REG_BANK_OFFSET COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_DEBUG_AUTH_PK_HASH_REG_BANK_OFFSET_bit_cg with function sample(input bit reg_bit);
/*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
Expand All @@ -1019,16 +989,16 @@
}

endgroup
covergroup soc_ifc_reg__CPTRA_DEBUG_AUTH_PK_HASH_REG_BANK_OFFSET_fld_cg with function sample(
input bit [32-1:0] offset
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_fld_cg with function sample(
input bit [32-1:0] hash
);
option.per_instance = 1;
offset_cp : coverpoint offset;
hash_cp : coverpoint hash;

endgroup

/*----------------------- SOC_IFC_REG__CPTRA_NUM_OF_DEBUG_AUTH_PK_HASHES COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_NUM_OF_DEBUG_AUTH_PK_HASHES_bit_cg with function sample(input bit reg_bit);
/*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH_LOCK COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
Expand All @@ -1039,11 +1009,11 @@
}

endgroup
covergroup soc_ifc_reg__CPTRA_NUM_OF_DEBUG_AUTH_PK_HASHES_fld_cg with function sample(
input bit [32-1:0] num
covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_fld_cg with function sample(
input bit [1-1:0] lock
);
option.per_instance = 1;
num_cp : coverpoint num;
lock_cp : coverpoint lock;

endgroup

Expand Down Expand Up @@ -1355,26 +1325,6 @@

endgroup

/*----------------------- SOC_IFC_REG__FUSE_PROD_DBG_UNLOCK_TOKEN COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__fuse_prod_dbg_unlock_token_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
}
reg_bit_edge_cp : coverpoint reg_bit {
bins rise = (0 => 1);
bins fall = (1 => 0);
}

endgroup
covergroup soc_ifc_reg__fuse_prod_dbg_unlock_token_fld_cg with function sample(
input bit [32-1:0] token
);
option.per_instance = 1;
token_cp : coverpoint token;

endgroup

/*----------------------- SOC_IFC_REG__SS_SOC_IFC_BASE_ADDR_L COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__SS_SOC_IFC_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
Expand Down Expand Up @@ -1575,8 +1525,28 @@

endgroup

/*----------------------- SOC_IFC_REG__SS_SOC_NONCE COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__SS_SOC_NONCE_bit_cg with function sample(input bit reg_bit);
/*----------------------- SOC_IFC_REG__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
}
reg_bit_edge_cp : coverpoint reg_bit {
bins rise = (0 => 1);
bins fall = (1 => 0);
}

endgroup
covergroup soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET_fld_cg with function sample(
input bit [32-1:0] offset
);
option.per_instance = 1;
offset_cp : coverpoint offset;

endgroup

/*----------------------- SOC_IFC_REG__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
Expand All @@ -1587,11 +1557,11 @@
}

endgroup
covergroup soc_ifc_reg__SS_SOC_NONCE_fld_cg with function sample(
input bit [32-1:0] nonce
covergroup soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES_fld_cg with function sample(
input bit [32-1:0] num
);
option.per_instance = 1;
nonce_cp : coverpoint nonce;
num_cp : coverpoint num;

endgroup

Expand Down Expand Up @@ -1715,6 +1685,26 @@

endgroup

/*----------------------- SOC_IFC_REG__SS_GENERIC_FW_EXEC_CTRL COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
}
reg_bit_edge_cp : coverpoint reg_bit {
bins rise = (0 => 1);
bins fall = (1 => 0);
}

endgroup
covergroup soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL_fld_cg with function sample(
input bit [32-1:0] go
);
option.per_instance = 1;
go_cp : coverpoint go;

endgroup

/*----------------------- SOC_IFC_REG__INTERNAL_OBF_KEY COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__internal_obf_key_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
Expand Down
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