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Use cmd line arg to build covergroups/sample include files
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calebofearth committed Nov 13, 2024
1 parent 89a3630 commit c1f9dce
Showing 1 changed file with 9 additions and 5 deletions.
14 changes: 9 additions & 5 deletions tools/scripts/reg_gen.py
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,9 @@

#output directory for dumping files
rtl_output_dir = os.path.abspath(os.path.dirname(sys.argv[1]))
build_cov = 0
if len(sys.argv) >= 2 and sys.argv[2] == "--cov":
build_cov = 1
repo_root = os.environ.get('CALIPTRA_ROOT')

# Listener to retrieve the address width at the CPU IF and write as a param to the pkg
Expand Down Expand Up @@ -103,11 +106,12 @@ def get_regfile_name(self):
exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_uvm.sv")
# The below lines are used to generate a baseline/starting point for the include files "<reg_name>_covergroups.svh" and "<reg_name>_sample.svh"
# The generated files will need to be hand-edited to provide the desired functionality.
# Uncomment these lines and run this script directly on the target RDL file to generate the files.
# exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/cov"))
# exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_covergroups.svh")
# exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/smp"))
# exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_sample.svh")
# Run this script directly on the target RDL file, with the second argument "--cov" to generate the files.
if build_cov == 1:
exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/cov"))
exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_covergroups.svh")
exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/smp"))
exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_sample.svh")

# Traverse the register model!
walker = RDLWalker(unroll=True)
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