Merge pull request #195 from chipsalliance/dev-msft-20230825

Dev msft 20230825
chipsalliance · Aug 26, 2023 · 4c52351 · 4c52351
2 parents d5b0ed4 + 5c684ee
commit 4c52351
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diff --git a/README.md b/README.md
@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2023/08/24*_
+_*Last Update: 2023/08/25*_
 
 
 ## **Tools Used** ##

diff --git a/Release_Notes.md b/Release_Notes.md
@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2023/08/24*_
+_*Last Update: 2023/08/25*_
 
 ## Rev 0p8 ##
 

diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c
@@ -188,6 +188,10 @@ void caliptra_rt() {
                 // If we entered the error state, we must use force-unlock to reset the mailbox state
                 state = (lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK) >> MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW;
                 if (state == MBOX_ERROR) {
+                    // clr command interrupt to avoid attempted re-processing after force-unlock
+                    if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+                        cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+                    }
                     lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
                 }
             }
@@ -348,11 +352,10 @@ void caliptra_rt() {
                     }
                     else {
                         // Read provided data
-                        for (loop_iter = 0; loop_iter<op.dlen; loop_iter+=4) {
+                        read_data = soc_ifc_mbox_read_dataout_single();
+                        temp      = soc_ifc_mbox_read_dataout_single(); // Capture resp dlen
+                        for (loop_iter = 8; loop_iter<op.dlen; loop_iter+=4) {
                             read_data = soc_ifc_mbox_read_dataout_single();
-                            if (loop_iter == 4) {
-                                temp = read_data; // Capture resp dlen
-                            }
                         }
 
                         // Set resp dlen

diff --git a/...plate_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh b/...plate_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
@@ -238,11 +238,11 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
 //    join
     fork
         forever begin
-            if (!std::randomize(mbox_ecc_single_error_burst,mbox_ecc_single_error_delay_clocks) with {mbox_ecc_single_error_burst        dist {1 :/ 1000, [2:5] :/ 100, [6:31] :/ 20, [32:131071] :/ 1, [131072:524288] :/ 1};
+            if (!std::randomize(mbox_ecc_single_error_burst,mbox_ecc_single_error_delay_clocks) with {mbox_ecc_single_error_burst        dist {1 :/ 10000, [2:5] :/ 2000, [6:31] :/ 200, [32:1023] :/ 10, [1024:131071] :/ 2, [131072:524288] :/ 1};
                                                                                                       mbox_ecc_single_error_delay_clocks dist {1 :/ 1, [2:31] :/ 3, [32:127] :/ 5, [128:1023] :/ 3, [1024:131072] :/ 1};    })
                 `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "Failed to randomize mbox ecc bit flip injection parameters")
             else
-                `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Randomized mbox ecc bit flip injection parameters: burst [%0d] delay [%0d clocks]", mbox_ecc_single_error_burst, mbox_ecc_single_error_delay_clocks), UVM_DEBUG)
+                `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Randomized mbox ecc bit flip injection parameters: burst [%0d] delay [%0d clocks]", mbox_ecc_single_error_burst, mbox_ecc_single_error_delay_clocks), UVM_FULL)
             soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(mbox_ecc_single_error_delay_clocks);
             `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Injecting mbox ecc error with burst [%0d]", mbox_ecc_single_error_burst), UVM_DEBUG)
             repeat(mbox_ecc_single_error_burst) begin

diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv
@@ -115,8 +115,6 @@ logic [MBOX_ECC_DATA_W-1:0] sram_rdata_cor_ecc;
 logic sram_we;
 logic mbox_protocol_sram_we;
 logic mbox_protocol_sram_rd, mbox_protocol_sram_rd_f;
-logic sram_ecc_cor_we;
-logic [$clog2(DEPTH)-1:0] sram_ecc_cor_waddr;
 logic dir_req_dv_q, dir_req_rd_phase;
 logic dir_req_wr_ph;
 logic mask_rdata;
@@ -273,6 +271,7 @@ always_comb begin : mbox_fsm_combo
                 mbox_fsm_ns = MBOX_IDLE;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         MBOX_RDY_FOR_DLEN: begin
@@ -287,6 +286,7 @@ always_comb begin : mbox_fsm_combo
                 mbox_fsm_ns = MBOX_IDLE;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         MBOX_RDY_FOR_DATA: begin
@@ -310,8 +310,11 @@ always_comb begin : mbox_fsm_combo
             end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
+                inc_wrptr = 0;
+                inc_rdptr = 0;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         //SoC set execute, data is for the uC
@@ -337,8 +340,11 @@ always_comb begin : mbox_fsm_combo
             end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
+                inc_wrptr = 0;
+                inc_rdptr = 0;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         //uC set execute, data is for the SoC
@@ -364,12 +370,15 @@ always_comb begin : mbox_fsm_combo
             end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
+                inc_wrptr = 0;
+                inc_rdptr = 0;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         MBOX_ERROR: begin
-            mbox_protocol_error_nxt = '0;
+            mbox_protocol_error_nxt = '{default: 0};
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
                 rst_mbox_wrptr = 1;
@@ -407,7 +416,6 @@ always_ff @(posedge clk or negedge rst_b) begin
         mbox_rdptr <= '0;
         mbox_rd_full <= '0;
         mbox_protocol_sram_rd_f <= '0;
-        sram_ecc_cor_waddr <= '0;
         dlen_in_dws <= '0;
         mbox_protocol_error <= '0;
         sram_rd_ecc_en <= '0;
@@ -423,8 +431,6 @@ always_ff @(posedge clk or negedge rst_b) begin
         mbox_protocol_sram_rd_f <= (mbox_protocol_sram_rd | mbox_protocol_sram_rd_f) ? mbox_protocol_sram_rd : mbox_protocol_sram_rd_f;
         mbox_rd_full <= (inc_rdptr | rst_mbox_rdptr) ? mbox_rd_full_nxt : mbox_rd_full;
         mbox_rd_valid_f <= (mbox_rd_valid | mbox_rd_valid_f) ? mbox_rd_valid : mbox_rd_valid_f;
-        sram_ecc_cor_waddr <= /*dir_req_rd_phase ? sram_ecc_cor_waddr :*/
-                                                 sram_rdaddr;
 
         dlen_in_dws <= latch_dlen_in_dws ? dlen_in_dws_nxt : dlen_in_dws;                    
         mbox_protocol_error <= mbox_protocol_error_nxt;
@@ -449,28 +455,26 @@ always_comb req_hold = (dir_req_dv_q & ~req_data.write) |
                        (dir_req_dv & sha_sram_req_dv) |
                        (hwif_out.mbox_dataout.dataout.swacc & mbox_protocol_sram_rd_f);
 
-always_comb sha_sram_hold = sram_single_ecc_error/* || sram_ecc_cor_we*/;
+always_comb sha_sram_hold = 1'b0;
 
 //SRAM interface
-always_comb sram_ecc_cor_we = sram_single_ecc_error; // TODO we probably want this to be a reg-stage to reduce combo logic SRAM -> rdata -> wdata -> SRAM
-always_comb sram_we = dir_req_wr_ph | mbox_protocol_sram_we | sram_ecc_cor_we;
+always_comb sram_we = dir_req_wr_ph | mbox_protocol_sram_we;
 //align the direct address to a word
 always_comb sram_rdaddr = dir_req_dv_q ? dir_req_addr : 
                           rst_mbox_rdptr ? 'd0 : mbox_rdptr;
-always_comb sram_waddr = sram_ecc_cor_we ? sram_ecc_cor_waddr :
-                         dir_req_dv_q    ? dir_req_addr : mbox_wrptr;
+always_comb sram_waddr = dir_req_dv_q    ? dir_req_addr : mbox_wrptr;
 //data phase after request for direct access
 //We want to mask the read data for certain accesses
 always_comb rdata = ({DATA_W{~mask_rdata}} & csr_rdata);
 always_comb dir_rdata = dir_req_rd_phase ? sram_rdata_cor : '0;
 
 always_comb begin: mbox_sram_inf
     //read live on direct access, or when pointer has been incremented, for pre-load on read pointer reset, or ecc correction
-    mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd | sram_ecc_cor_we;
+    mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd;
     mbox_sram_req.we = sram_we;
     mbox_sram_req.addr = sram_we ? sram_waddr : sram_rdaddr;
-    mbox_sram_req.wdata.data = sram_ecc_cor_we ? sram_rdata_cor     : sram_wdata;
-    mbox_sram_req.wdata.ecc  = sram_ecc_cor_we ? sram_rdata_cor_ecc : sram_wdata_ecc;
+    mbox_sram_req.wdata.data = sram_wdata;
+    mbox_sram_req.wdata.ecc  = sram_wdata_ecc;
 
     sram_rdata     = mbox_sram_resp.rdata.data;
     sram_rdata_ecc = mbox_sram_resp.rdata.ecc;
@@ -593,7 +597,7 @@ mbox_csr1(
     .hwif_out(hwif_out)
 );
 
-`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd | sram_ecc_cor_we}, clk, rst_b)
+`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q , mbox_protocol_sram_we , mbox_protocol_sram_rd }, clk, rst_b)
 `CALIPTRA_ASSERT_MUTEX(ERR_MBOX_DIR_SHA_COLLISION, {dir_req_dv, sha_sram_req_dv}, clk, rst_b)
 `CALIPTRA_ASSERT_NEVER(ERR_MBOX_DIR_REQ_FROM_SOC, (dir_req_dv & req_data.soc_req), clk, rst_b)
 

diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv
@@ -70,6 +70,14 @@ package soc_ifc_pkg;
     parameter DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG = 7'h60;
     parameter DMI_REG_BOOTFSM_GO = 7'h61;
 
+    // This parameter describes the hard-coded implementation in the BOOT FSM
+    // that results in noncore reset assertion being delayed from the soft reset
+    // (cptra_rst_b) by some integer number of clock cycles, due to synchronization
+    // stages and the rst window signaling.
+    // This is useful in validation environments for controlling the predicted
+    // timing in a reset event.
+    parameter SOC_IFC_CPTRA_RST_NONCORE_RST_DELAY = 4;
+
     //BOOT FSM
     typedef enum logic [2:0] {
         BOOT_IDLE   = 3'b000,

diff --git a/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml b/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
@@ -17,4 +17,5 @@ plusargs:
   - +SOC_IFC_TEST='fuse_reg_perm_test'
 
 testname: fuse_reg_perm_test 
-seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: ${PLAYBOOK_RANDOM_SEED}
+seed: 1692834441
diff --git a/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml b/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
@@ -18,3 +18,4 @@ plusargs:
 
 testname: soc_reg_intrblk_test
 seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: 1692153169 
diff --git a/src/soc_ifc/tb/fuse_reg_perm_test.svh b/src/soc_ifc/tb/fuse_reg_perm_test.svh
@@ -52,11 +52,13 @@ any subsequent writes to a fuse register will be dropped unless
 
     init_sim();
     reset_dut();
+    wait(ready_for_fuses);
 
     // -----------------------------------------------------------------
     // PHASE 1. Normal sequence 
     // -----------------------------------------------------------------
     $display ("1a. APB write twice to registers, lock fuses and attempt to modify\n");
+    tphase = "1a";
 
     write_regs(SET_APB, fuse_regnames, 0, 3);  // effect changes
     repeat (5) @(posedge clk_tb);
@@ -74,6 +76,7 @@ any subsequent writes to a fuse register will be dropped unless
     repeat (5) @(posedge clk_tb);
 
     $display ("\n1b. Following writes should have no effect on locked state -- which is still set!\n");
+    tphase = "1b";
 
     sb.del_all();
 
@@ -88,11 +91,14 @@ any subsequent writes to a fuse register will be dropped unless
     // -----------------------------------------------------------------
     // PHASE 2. Perform Cold Reset and Repeat APB Write & Read from 1a  
     // -----------------------------------------------------------------
+    $display ("\n2a. Write to registers after cold boot and check back writes");
+    tphase = "2a";
+
     reset_dut(); // expect to be clearing CPTRA_FUSE_WR_DONE effect 
     reset_exp_data();
     sb.del_all();
-
-    $display ("\n2a. Write to registers after cold boot and check back writes");
+    wait(ready_for_fuses);
+    @(posedge clk_tb);
 
     write_regs(SET_APB, fuse_regnames, 0, 3);
     read_regs(GET_APB, fuse_regnames, 0, 3);
@@ -107,9 +113,12 @@ any subsequent writes to a fuse register will be dropped unless
     // PHASE 3. Perform Warm Reset, read values & Repeat APB Write & Read from 1a  
     // -----------------------------------------------------------------
     $display ("\n3a. Perform a warm reset then repeat steps 1a (just APB)"); 
+    tphase = "3a";
 
     warm_reset_dut(); 
     warm_reset_exp_data();
+    wait(ready_for_fuses);
+    @(posedge clk_tb);
 
     read_regs(GET_APB, fuse_regnames, 0, 3);      // should be old sticky values
     sb.del_all();

diff --git a/src/soc_ifc/tb/soc_ifc_tb.sv b/src/soc_ifc/tb/soc_ifc_tb.sv
@@ -169,10 +169,13 @@ module soc_ifc_tb
 
   bit            reg_sva_off = 1'b1;  // Enable only during register assertion checks
 
+  logic [APB_DATA_WIDTH-1:0]    prdata_o_latched;
 
 
-
-
+  always @(negedge clk_tb) begin
+    prdata_o_latched <= prdata_o_tb;
+  end
+
   always_comb begin
     mbox_sram_cs = mbox_sram_req.cs;
     mbox_sram_we = mbox_sram_req.we;
@@ -446,6 +449,7 @@ module soc_ifc_tb
       repeat (5) @(posedge clk_tb);
 
       cptra_rst_b_tb = 1;
+      repeat (5) @(posedge clk_tb);
       $display("");
     end
   endtask // reset_dut
@@ -468,6 +472,7 @@ module soc_ifc_tb
       repeat (5) @(posedge clk_tb);
 
       cptra_rst_b_tb = 1;
+      repeat (5) @(posedge clk_tb);
       $display("");
     end
   endtask // reset_dut
@@ -1262,12 +1267,14 @@ module soc_ifc_tb
         if (modifier == GET_AHB) begin
           read_single_word_ahb(addr);
           valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO]; 
-          $display(" Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, valid_hrdata); 
+          $display(" Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x on cycle %08d", rname, addr, valid_hrdata, cycle_ctr); 
           rdtrans.update(addr, valid_hrdata, tid); 
         end else if (modifier == GET_APB) begin
           read_single_word_apb(addr);
-          $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); 
-          rdtrans.update(addr, prdata_o_tb, tid); 
+          // $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x at time %12t (cycle %08d)", rname, addr, prdata_o_latched, $realtime, cycle_ctr); // used to be   prdata_o_tb
+          $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x on cycle %08d", rname, addr, prdata_o_tb, cycle_ctr); // used to be   prdata_o_tb
+          // rdtrans.update(addr, prdata_o_latched, tid);  // used to be prdata_o_tb
+          rdtrans.update(addr, prdata_o_tb, tid);  
         end else 
           $error("TB ERROR. Unsupported access modifier %s", modifier.name());
Original file line number	Diff line number	Diff line change
Expand Up		@@ -18,3 +18,4 @@ plusargs:

		testname: soc_reg_intrblk_test
		seed: ${PLAYBOOK_RANDOM_SEED}
		# seed: 1692153169