adding tap interface to new registers

chipsalliance · Nov 17, 2024 · 1614171 · 1614171
1 parent dcc5525
commit 1614171
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Showing 13 changed files with 407 additions and 96 deletions.
diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
@@ -195,7 +195,10 @@ module caliptra_top
     //caliptra uncore jtag ports & pertinent logic
     logic                       cptra_core_dmi_enable;
     logic                       cptra_uncore_dmi_enable;
+    logic                       cptra_mbox_dmi_enable;
     logic                       cptra_uncore_dmi_reg_en;
+    logic                       cptra_uncore_dmi_unlocked_reg_en;
+    logic                       cptra_uncore_dmi_locked_reg_en;
     logic                       cptra_uncore_dmi_reg_wr_en;
     logic [31:0]                cptra_uncore_dmi_reg_rdata;
     logic [6:0]                 cptra_uncore_dmi_reg_addr;
@@ -413,9 +416,19 @@ always_comb begin
     intr[NUM_INTR-1:`VEER_INTR_VEC_MAX_ASSIGNED]  = '0;
 end
 
-always_comb cptra_core_dmi_enable = ~(cptra_security_state_Latched.debug_locked); 
+//Open Core TAP only for debug unlocked
+always_comb cptra_core_dmi_enable = ~(cptra_security_state_Latched.debug_locked);
+//Open Uncore TAP for debug unlocked, or DEVICE_MANUFACTURING, or debug intent set
 always_comb cptra_uncore_dmi_enable = ~(cptra_security_state_Latched.debug_locked) | 
-                                      ((cptra_security_state_Latched.debug_locked) & (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING));
+                                       (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING) |
+                                       ss_debug_intent;
+
+//Uncore registers only open for debug unlock or manufacturing
+always_comb cptra_uncore_dmi_unlocked_reg_en = cptra_uncore_dmi_reg_en & 
+                                               (~(cptra_security_state_Latched.debug_locked) | 
+                                                 (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING));
+//Uncore registers open for all cases
+always_comb cptra_uncore_dmi_locked_reg_en = cptra_uncore_dmi_reg_en;
 
 el2_veer_wrapper rvtop (
 `ifdef CALIPTRA_FORCE_CPU_RESET
@@ -1283,7 +1296,8 @@ soc_ifc_top1
     //multiple cryptos operating at once, assert fatal error
     .crypto_error(crypto_error),
     //caliptra uncore jtag ports
-    .cptra_uncore_dmi_reg_en   ( cptra_uncore_dmi_reg_en ),
+    .cptra_uncore_dmi_unlocked_reg_en( cptra_uncore_dmi_unlocked_reg_en ),
+    .cptra_uncore_dmi_locked_reg_en( cptra_uncore_dmi_locked_reg_en ),
     .cptra_uncore_dmi_reg_wr_en( cptra_uncore_dmi_reg_wr_en ),
     .cptra_uncore_dmi_reg_rdata( cptra_uncore_dmi_reg_rdata ),
     .cptra_uncore_dmi_reg_addr ( cptra_uncore_dmi_reg_addr ),

diff --git a/src/integration/test_suites/caliptra_demo/caliptra_demo.c b/src/integration/test_suites/caliptra_demo/caliptra_demo.c
@@ -267,7 +267,7 @@ void mbox_fw() {
     uint32_t data;
 
     //set ready for FW
-    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
     // Roughly equivalent to .rept 99 "nop" since the loop requires 3 (5?) ops each iteration
     // nop

diff --git a/src/integration/test_suites/caliptra_top/caliptra_top.c b/src/integration/test_suites/caliptra_top/caliptra_top.c
@@ -81,7 +81,7 @@ void main() {
         doe_init(iv_data_uds, iv_data_fe, 0x6); // TODO replace 0x6 with entry indicators
 
         VPRINTF(LOW, "Setting Flow Status\n");
-        soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+        soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
         VPRINTF(LOW, "Unlocking SHA512-ACC\n");
         // Clear SHA accelerator lock (FIPS requirement)
@@ -150,7 +150,7 @@ void main() {
         }
 
         // Clear 'ready for fw'
-        soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+        soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
         // Jump to ICCM (this is the FMC image, a.k.a. Section 0)
         VPRINTF(LOW, "FMC FW loaded into ICCM - jumping there \n");
@@ -177,7 +177,7 @@ void main() {
         // skip doe_init
 
         // Ready for FW (need to reload the FMC)
-        soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+        soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
         // Clear SHA accelerator lock (FIPS requirement)
         soc_ifc_w1clr_sha_lock_field(SHA512_ACC_CSR_LOCK_LOCK_MASK);
@@ -217,7 +217,7 @@ void main() {
         }
 
         // Clear 'ready for fw'
-        soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+        soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
         // Jump to ICCM (this is the FMC image, a.k.a. Section 0)
         iccm_fmc();

diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c
@@ -123,7 +123,7 @@ void main() {
                       : "i" (0x304), "r" (mie_machinetimer_en)  /* input : immediate  */ \
                       : /* clobbers: none */);
 
-        *soc_ifc_flow_status = SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK;
+        *soc_ifc_flow_status = SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK;
 
         //Halt the core
         __asm__ volatile ("csrwi    %0, %1" \

diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s
@@ -124,7 +124,7 @@ _start:
     //TODO: how to write a dword in asm
     //Trigger APB tx
     li x3, CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS
-    li x4, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK
+    li x4, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK
     //sb x5, 0(x3)
 
     loop1:

diff --git a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
@@ -53,7 +53,7 @@ void main () {
     VPRINTF(LOW, "----------------------------------\n");
 
     //set ready for FW so tb will push FW
-    soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+    soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
     // Sleep
     for (uint16_t slp = 0; slp < 33; slp++);

diff --git a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c
@@ -119,7 +119,7 @@ void main () {
     SEND_STDOUT_CTRL(0xf2);
 
     //set ready for FW so tb will push FW
-    soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+    soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
 
     set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
 

diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv
@@ -74,10 +74,30 @@ package soc_ifc_pkg;
     parameter DMI_REG_BOOT_STATUS = 7'h53;
     parameter DMI_REG_CPTRA_HW_ERRROR_ENC = 7'h54;
     parameter DMI_REG_CPTRA_FW_ERROR_ENC = 7'h55;
-    parameter DMI_REG_MBOX_DIN = 7'h56;
+    parameter DMI_REG_SS_UDS_SEED_BASE_ADDR_L = 7'h56;
+    parameter DMI_REG_SS_UDS_SEED_BASE_ADDR_H = 7'h57;
     //RW registers
     parameter DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG = 7'h60;
     parameter DMI_REG_BOOTFSM_GO = 7'h61;
+    parameter DMI_REG_MBOX_DIN = 7'h62;
+    parameter DMI_REG_SS_DEBUG_INTENT = 7'h63;
+    parameter DMI_REG_SS_SOC_IFC_BASE_ADDR_L = 7'h64;
+    parameter DMI_REG_SS_SOC_IFC_BASE_ADDR_H = 7'h65;
+    parameter DMI_REG_SS_MCI_BASE_ADDR_L = 7'h66;
+    parameter DMI_REG_SS_MCI_BASE_ADDR_H = 7'h67;
+    parameter DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_L = 7'h68;
+    parameter DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_H = 7'h69;
+    parameter DMI_REG_SS_OTP_FC_BASE_ADDR_L = 7'h6A;
+    parameter DMI_REG_SS_OTP_FC_BASE_ADDR_H = 7'h6B;
+    parameter DMI_REG_SS_STRAP_RSVD_0 = 7'h6C;
+    parameter DMI_REG_SS_STRAP_RSVD_1 = 7'h6D;
+    parameter DMI_REG_SS_STRAP_RSVD_2 = 7'h6E;
+    parameter DMI_REG_SS_STRAP_RSVD_3 = 7'h6F;
+    parameter DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ = 7'h70;
+    parameter DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP = 7'h71;
+    parameter DMI_REG_SS_DBG_UNLOCK_LEVEL0 = 7'h72;
+    parameter DMI_REG_SS_DBG_UNLOCK_LEVEL1 = 7'h73;
+
 
     // This parameter describes the hard-coded implementation in the BOOT FSM
     // that results in noncore reset assertion being delayed from the soft reset