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refactor(Frontend): rename bundles & reorganize IO with Ifu/Ftq
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 Naming:
- I/O:
  - ICache inner use only: xxxBundle
  - Other modules use: ICacheXxxBundle, consider move to FrontendBundle.scala
- Sram/register: xxxEntry

Try avoiding directed Bundle, unless it's req-resp pair

Add ICacheToIfuIO & move resp/perf/topdown/icacheReady into it
- ICacheIO.toIFU / IFUICacheIO.icacheReady -> ICacheToIfuIO.fetchReady
- ICacheIO.perfInfo / NewIFUIO.icachePerfInfo -> ICacheToIfuIO.perf
- ICacheMainPipeBundle.topdown.* / IFUICacheIO.topdown* -> ICacheToIfuIO.topdown.*

Add IfuToICacheIO & move stall into it
- NewIFUIO.icacheStop / ICacheIO.stop -> IfuToICacheIO.stall

Add FtqToICacheIO
- ICacheIO.fetch -> FtqToICacheIO.fetchReq
- ICacheIO.ftqPrefetch / FtqToPrefetchIO -> FtqToICacheIO.prefetchReq

Other renames
- ICacheIO.softPrefetch -> ICacheIO.softPrefetchReq
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@ngc7331
ngc7331 committed Mar 3, 2025
1 parent ccf6048 commit 14804c4
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Showing 15 changed files with 546 additions and 504 deletions.
29 changes: 13 additions & 16 deletions src/main/scala/xiangshan/frontend/Frontend.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -165,35 +165,32 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
val itlbRepeater2 =
PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, io.ptw, sfence, tlbCsr)

icache.io.ftqPrefetch <> ftq.io.toPrefetch
icache.io.softPrefetch <> io.softPrefetch
// ICache-Memblock
icache.io.softPrefetchReq <> io.softPrefetch

// IFU-Ftq
ifu.io.ftqInter.fromFtq <> ftq.io.toIfu
ftq.io.toIfu.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready
ftq.io.toIfu.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fromFtq.fetchReq.ready

ftq.io.fromIfu <> ifu.io.ftqInter.toFtq
bpu.io.ftq_to_bpu <> ftq.io.toBpu
ftq.io.fromBpu <> bpu.io.bpu_to_ftq

ftq.io.mmioCommitRead <> ifu.io.mmioCommitRead

// IFU-ICache
icache.io.fetch.req <> ftq.io.toICache.req
ftq.io.toICache.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready
// ICache-Ftq
icache.io.fromFtq <> ftq.io.toICache
// override fetchReq.ready to sync with Ifu
ftq.io.toICache.fetchReq.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fromFtq.fetchReq.ready
icache.io.flush := ftq.io.icacheFlush

ifu.io.icacheInter.resp <> icache.io.fetch.resp
ifu.io.icacheInter.icacheReady := icache.io.toIFU
ifu.io.icacheInter.topdownIcacheMiss := icache.io.fetch.topdownIcacheMiss
ifu.io.icacheInter.topdownItlbMiss := icache.io.fetch.topdownItlbMiss
icache.io.stop := ifu.io.icacheStop
icache.io.flush := ftq.io.icacheFlush

ifu.io.icachePerfInfo := icache.io.perfInfo
// Ifu-ICache
ifu.io.fromICache <> icache.io.toIfu
ifu.io.toICache <> icache.io.fromIfu

// ICache-Backend
icache.io.csr_pf_enable := RegNext(csrCtrl.pf_ctrl.l1I_pf_enable)

icache.io.fencei := RegNext(io.fencei)
icache.io.fencei := RegNext(io.fencei)

// IFU-Ibuffer
ifu.io.toIbuffer <> ibuffer.io.in
Expand Down
35 changes: 26 additions & 9 deletions src/main/scala/xiangshan/frontend/FrontendBundle.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -78,17 +78,34 @@ class FtqICacheInfo(implicit p: Parameters) extends XSBundle with HasICacheParam
}
}

class IFUICacheIO(implicit p: Parameters) extends XSBundle with HasICacheParameters {
val icacheReady = Output(Bool())
val resp = ValidIO(new ICacheMainPipeResp)
val topdownIcacheMiss = Output(Bool())
val topdownItlbMiss = Output(Bool())
class FtqToPrefetchBundle(implicit p: Parameters) extends XSBundle {
val req: FtqICacheInfo = new FtqICacheInfo
val backendException: UInt = ExceptionType()
}

class FtqToICacheRequestBundle(implicit p: Parameters) extends XSBundle with HasICacheParameters {
val pcMemRead = Vec(5, new FtqICacheInfo)
val readValid = Vec(5, Bool())
val backendException = Bool()
class FtqToFetchBundle(implicit p: Parameters) extends XSBundle with HasICacheParameters {
val req: Vec[FtqICacheInfo] = Vec(5, new FtqICacheInfo)
val readValid: Vec[Bool] = Vec(5, Bool())
val isBackendException: Bool = Bool()
}

class FtqToICacheIO(implicit p: Parameters) extends XSBundle {
// NOTE: req.bits must be prepare in T cycle
// while req.valid is set true in T + 1 cycle
val fetchReq: DecoupledIO[FtqToFetchBundle] = DecoupledIO(new FtqToFetchBundle)
val prefetchReq: DecoupledIO[FtqToPrefetchBundle] = DecoupledIO(new FtqToPrefetchBundle)
val flushFromBpu: BpuFlushInfo = new BpuFlushInfo
}

class ICacheToIfuIO(implicit p: Parameters) extends XSBundle {
val fetchResp: Valid[ICacheRespBundle] = ValidIO(new ICacheRespBundle)
val topdown: ICacheTopdownInfo = Output(new ICacheTopdownInfo)
val perf: ICachePerfInfo = Output(new ICachePerfInfo)
val fetchReady: Bool = Output(Bool())
}

class IfuToICacheIO(implicit p: Parameters) extends XSBundle {
val stall: Bool = Output(Bool())
}

class PredecodeWritebackBundle(implicit p: Parameters) extends XSBundle {
Expand Down
21 changes: 10 additions & 11 deletions src/main/scala/xiangshan/frontend/IFU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -69,16 +69,15 @@ class UncacheInterface(implicit p: Parameters) extends XSBundle {

class NewIFUIO(implicit p: Parameters) extends XSBundle {
val ftqInter = new FtqInterface
val icacheInter = Flipped(new IFUICacheIO)
val icacheStop = Output(Bool())
val icachePerfInfo = Input(new ICachePerfInfo)
val fromICache = Flipped(new ICacheToIfuIO)
val toICache = new IfuToICacheIO
val toIbuffer = Decoupled(new FetchToIBuffer)
val toBackend = new IfuToBackendIO
val uncacheInter = new UncacheInterface
val frontendTrigger = Flipped(new FrontendTdataDistributeIO)
val rob_commits = Flipped(Vec(CommitWidth, Valid(new RobCommitInfo)))
val iTLBInter = new TlbRequestIO
val pmp = new ICachePMPBundle
val pmp = new PmpCheckBundle
val mmioCommitRead = new mmioCommitRead
val csr_fsIsOff = Input(Bool())
}
Expand Down Expand Up @@ -137,7 +136,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
with HasTlbConst {
val io = IO(new NewIFUIO)
val (toFtq, fromFtq) = (io.ftqInter.toFtq, io.ftqInter.fromFtq)
val fromICache = io.icacheInter.resp
val fromICache = io.fromICache.fetchResp
val (toUncache, fromUncache) = (io.uncacheInter.toUncache, io.uncacheInter.fromUncache)

def isCrossLineReq(start: UInt, end: UInt): Bool = start(blockOffBits) ^ end(blockOffBits)
Expand Down Expand Up @@ -260,7 +259,7 @@ class NewIFU(implicit p: Parameters) extends XSModule

val f1_ready, f2_ready, f3_ready = WireInit(false.B)

fromFtq.req.ready := f1_ready && io.icacheInter.icacheReady
fromFtq.req.ready := f1_ready && io.fromICache.fetchReady

when(wb_redirect) {
when(f3_wb_not_flush) {
Expand Down Expand Up @@ -371,10 +370,10 @@ class NewIFU(implicit p: Parameters) extends XSModule

icacheRespAllValid := f2_icache_all_resp_reg || f2_icache_all_resp_wire

icacheMissBubble := io.icacheInter.topdownIcacheMiss
itlbMissBubble := io.icacheInter.topdownItlbMiss
icacheMissBubble := io.fromICache.topdown.icacheMiss
itlbMissBubble := io.fromICache.topdown.itlbMiss

io.icacheStop := !f3_ready
io.toICache.stall := !f3_ready

when(f2_flush)(f2_icache_all_resp_reg := false.B)
.elsewhen(f2_valid && f2_icache_all_resp_wire && !f3_ready)(f2_icache_all_resp_reg := true.B)
Expand All @@ -385,7 +384,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
.elsewhen(f2_fire)(f2_valid := false.B)

val f2_exception_in = fromICache.bits.exception
val f2_backendException = fromICache.bits.backendException
val f2_backendException = fromICache.bits.isBackendException
// paddr and gpaddr of [startAddr, nextLineAddr]
val f2_paddrs = fromICache.bits.paddr
val f2_gpaddr = fromICache.bits.gpaddr
Expand Down Expand Up @@ -453,7 +452,7 @@ class NewIFU(implicit p: Parameters) extends XSModule
)
)
))
val f2_perf_info = io.icachePerfInfo
val f2_perf_info = io.fromICache.perf

def cut(cacheline: UInt, cutPtr: Vec[UInt]): Vec[UInt] = {
require(HasCExtension)
Expand Down
62 changes: 27 additions & 35 deletions src/main/scala/xiangshan/frontend/NewFtq.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -211,18 +211,6 @@ class FtqToIfuIO(implicit p: Parameters) extends XSBundle {
val flushFromBpu = new BpuFlushInfo
}

class FtqToICacheIO(implicit p: Parameters) extends XSBundle {
// NOTE: req.bits must be prepare in T cycle
// while req.valid is set true in T + 1 cycle
val req = Decoupled(new FtqToICacheRequestBundle)
}

class FtqToPrefetchIO(implicit p: Parameters) extends XSBundle {
val req = Decoupled(new FtqICacheInfo)
val flushFromBpu = new BpuFlushInfo
val backendException = ExceptionType()
}

trait HasBackendRedirectInfo extends HasXSParameter {
def isLoadReplay(r: Valid[Redirect]) = r.bits.flushItself()
}
Expand Down Expand Up @@ -494,7 +482,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
val toIfu = new FtqToIfuIO
val toICache = new FtqToICacheIO
val toBackend = new FtqToCtrlIO
val toPrefetch = new FtqToPrefetchIO
val icacheFlush = Output(Bool())

val bpuInfo = new Bundle {
Expand Down Expand Up @@ -756,7 +743,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
ifuPtrPlus1_write := ifuPtrPlus2
ifuPtrPlus2_write := ifuPtrPlus2 + 1.U
}
when(io.toPrefetch.req.fire && allowToIfu) {
when(io.toICache.prefetchReq.fire && allowToIfu) {
pfPtr_write := pfPtrPlus1
pfPtrPlus1_write := pfPtrPlus1 + 1.U
}
Expand All @@ -766,10 +753,10 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
entry_hit_status(bpu_s2_resp.ftq_idx.value) := Mux(bpu_s2_resp.full_pred(3).hit, h_hit, h_not_hit)
}

io.toIfu.flushFromBpu.s2.valid := bpu_s2_redirect
io.toIfu.flushFromBpu.s2.bits := bpu_s2_resp.ftq_idx
io.toPrefetch.flushFromBpu.s2.valid := bpu_s2_redirect
io.toPrefetch.flushFromBpu.s2.bits := bpu_s2_resp.ftq_idx
io.toIfu.flushFromBpu.s2.valid := bpu_s2_redirect
io.toIfu.flushFromBpu.s2.bits := bpu_s2_resp.ftq_idx
io.toICache.flushFromBpu.s2.valid := bpu_s2_redirect
io.toICache.flushFromBpu.s2.bits := bpu_s2_resp.ftq_idx
when(bpu_s2_redirect) {
bpuPtr := bpu_s2_resp.ftq_idx + 1.U
copied_bpu_ptr.map(_ := bpu_s2_resp.ftq_idx + 1.U)
Expand All @@ -785,10 +772,10 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
}
}

io.toIfu.flushFromBpu.s3.valid := bpu_s3_redirect
io.toIfu.flushFromBpu.s3.bits := bpu_s3_resp.ftq_idx
io.toPrefetch.flushFromBpu.s3.valid := bpu_s3_redirect
io.toPrefetch.flushFromBpu.s3.bits := bpu_s3_resp.ftq_idx
io.toIfu.flushFromBpu.s3.valid := bpu_s3_redirect
io.toIfu.flushFromBpu.s3.bits := bpu_s3_resp.ftq_idx
io.toICache.flushFromBpu.s3.valid := bpu_s3_redirect
io.toICache.flushFromBpu.s3.bits := bpu_s3_resp.ftq_idx
when(bpu_s3_redirect) {
bpuPtr := bpu_s3_resp.ftq_idx + 1.U
copied_bpu_ptr.map(_ := bpu_s3_resp.ftq_idx + 1.U)
Expand Down Expand Up @@ -819,7 +806,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
val bpu_in_bypass_buf_for_ifu = bpu_in_bypass_buf
val bpu_in_bypass_ptr = RegEnable(bpu_in_resp_ptr, bpu_in_fire)
val last_cycle_to_ifu_fire = RegNext(io.toIfu.req.fire)
val last_cycle_to_pf_fire = RegNext(io.toPrefetch.req.fire)
val last_cycle_to_pf_fire = RegNext(io.toICache.prefetchReq.fire)

val copied_bpu_in_bypass_ptr = VecInit(Seq.fill(copyNum)(RegEnable(bpu_in_resp_ptr, bpu_in_fire)))
val copied_last_cycle_to_ifu_fire = VecInit(Seq.fill(copyNum)(RegNext(io.toIfu.req.fire)))
Expand Down Expand Up @@ -874,7 +861,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
when(bpu_in_fire && bpu_in_resp_ptr === pfPtr_write) {
nextCycleToPrefetchPcBundle := ftq_pc_mem.io.wdata
nextCycleToPrefetchEntryToSend := true.B
}.elsewhen(io.toPrefetch.req.fire) {
}.elsewhen(io.toICache.prefetchReq.fire) {
nextCycleToPrefetchPcBundle := ftq_pc_mem.io.pfPtrPlus1_rdata
nextCycleToPrefetchEntryToSend := entry_fetch_status(pfPtrPlus1.value) === f_to_send ||
last_cycle_bpu_in && bpu_in_bypass_ptr === pfPtrPlus1
Expand Down Expand Up @@ -916,22 +903,27 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
io.toIfu.req.bits.ftqOffset := entry_ftq_offset
io.toIfu.req.bits.fromFtqPcBundle(toIfuPcBundle)

io.toICache.req.valid := entry_is_to_send && ifuPtr =/= bpuPtr
io.toICache.req.bits.readValid.zipWithIndex.map { case (copy, i) =>
io.toICache.fetchReq.valid := entry_is_to_send && ifuPtr =/= bpuPtr
io.toICache.fetchReq.bits.readValid.zipWithIndex.map { case (copy, i) =>
copy := toICacheEntryToSend(i) && copied_ifu_ptr(i) =/= copied_bpu_ptr(i)
}
io.toICache.req.bits.pcMemRead.zipWithIndex.foreach { case (copy, i) =>
io.toICache.fetchReq.bits.req.zipWithIndex.foreach { case (copy, i) =>
copy.fromFtqPcBundle(toICachePcBundle(i))
copy.ftqIdx := ifuPtr
}
io.toICache.req.bits.backendException := ExceptionType.hasException(backendException) && backendPcFaultPtr === ifuPtr

io.toPrefetch.req.valid := toPrefetchEntryToSend && pfPtr =/= bpuPtr
io.toPrefetch.req.bits.fromFtqPcBundle(toPrefetchPcBundle)
io.toPrefetch.req.bits.ftqIdx := pfPtr
io.toPrefetch.backendException := Mux(backendPcFaultPtr === pfPtr, backendException, ExceptionType.none)
// io.toICache.req.bits.bypassSelect := last_cycle_bpu_in && bpu_in_bypass_ptr === ifuPtr
// io.toICache.req.bits.bpuBypassWrite.zipWithIndex.map{case(bypassWrtie, i) =>
io.toICache.fetchReq.bits.isBackendException :=
ExceptionType.hasException(backendException) && backendPcFaultPtr === ifuPtr

io.toICache.prefetchReq.valid := toPrefetchEntryToSend && pfPtr =/= bpuPtr
io.toICache.prefetchReq.bits.req.fromFtqPcBundle(toPrefetchPcBundle)
io.toICache.prefetchReq.bits.req.ftqIdx := pfPtr
io.toICache.prefetchReq.bits.backendException := Mux(
backendPcFaultPtr === pfPtr,
backendException,
ExceptionType.none
)
// io.toICache.fetchReq.bits.bypassSelect := last_cycle_bpu_in && bpu_in_bypass_ptr === ifuPtr
// io.toICache.fetchReq.bits.bpuBypassWrite.zipWithIndex.map{case(bypassWrtie, i) =>
// bypassWrtie.startAddr := bpu_in_bypass_buf.tail(i).startAddr
// bypassWrtie.nextlineStart := bpu_in_bypass_buf.tail(i).nextLineAddr
// }
Expand Down
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