Skip to content

Commit ccf6048

Browse files
ngc7331ngc7331
committed
refactor(Frontend): move module IO inside class & rename IPrefetch
1 parent 87e40bd commit ccf6048

9 files changed

+107
-112
lines changed

‎src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala

+11-11
Original file line numberDiff line numberDiff line change
@@ -29,17 +29,6 @@ import freechips.rocketchip.tilelink.TLRegisterNode
2929
import org.chipsalliance.cde.config.Parameters
3030
import utils.NamedUInt
3131

32-
class ICacheCtrlUnitIO(implicit p: Parameters) extends ICacheBundle {
33-
// ecc control
34-
val ecc_enable: Bool = Output(Bool())
35-
// ecc inject
36-
val injecting: Bool = Output(Bool())
37-
val metaRead: DecoupledIO[ICacheReadBundle] = DecoupledIO(new ICacheReadBundle)
38-
val metaReadResp: ICacheMetaRespBundle = Input(new ICacheMetaRespBundle)
39-
val metaWrite: DecoupledIO[ICacheMetaWriteBundle] = DecoupledIO(new ICacheMetaWriteBundle)
40-
val dataWrite: DecoupledIO[ICacheDataWriteBundle] = DecoupledIO(new ICacheDataWriteBundle)
41-
}
42-
4332
// currently for ECC control only
4433
class ICacheCtrlUnit(params: ICacheCtrlUnitParams)(implicit p: Parameters) extends LazyModule {
4534
lazy val module = new ICacheCtrlUnitImp(this)
@@ -55,6 +44,17 @@ class ICacheCtrlUnit(params: ICacheCtrlUnitParams)(implicit p: Parameters) exten
5544
)
5645

5746
class ICacheCtrlUnitImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasICacheParameters {
47+
class ICacheCtrlUnitIO(implicit p: Parameters) extends ICacheBundle {
48+
// ecc control
49+
val ecc_enable: Bool = Output(Bool())
50+
// ecc inject
51+
val injecting: Bool = Output(Bool())
52+
val metaRead: DecoupledIO[ICacheReadBundle] = DecoupledIO(new ICacheReadBundle)
53+
val metaReadResp: ICacheMetaRespBundle = Input(new ICacheMetaRespBundle)
54+
val metaWrite: DecoupledIO[ICacheMetaWriteBundle] = DecoupledIO(new ICacheMetaWriteBundle)
55+
val dataWrite: DecoupledIO[ICacheDataWriteBundle] = DecoupledIO(new ICacheDataWriteBundle)
56+
}
57+
5858
val io: ICacheCtrlUnitIO = IO(new ICacheCtrlUnitIO)
5959

6060
// eccctrl.ierror: inject error code

‎src/main/scala/xiangshan/frontend/icache/ICacheDataArray.scala

+8-8
Original file line numberDiff line numberDiff line change
@@ -20,13 +20,15 @@ import chisel3.util._
2020
import org.chipsalliance.cde.config.Parameters
2121
import utility.mbist.MbistPipeline
2222

23-
class ICacheDataArrayIO(implicit p: Parameters) extends ICacheBundle {
24-
val write: DecoupledIO[ICacheDataWriteBundle] = Flipped(DecoupledIO(new ICacheDataWriteBundle))
25-
val read: Vec[DecoupledIO[ICacheReadBundle]] = Flipped(Vec(partWayNum, DecoupledIO(new ICacheReadBundle)))
26-
val readResp: ICacheDataRespBundle = Output(new ICacheDataRespBundle)
27-
}
28-
2923
class ICacheDataArray(implicit p: Parameters) extends ICacheModule with ICacheECCHelper with ICacheDataSelHelper {
24+
class ICacheDataArrayIO(implicit p: Parameters) extends ICacheBundle {
25+
val write: DecoupledIO[ICacheDataWriteBundle] = Flipped(DecoupledIO(new ICacheDataWriteBundle))
26+
val read: Vec[DecoupledIO[ICacheReadBundle]] = Flipped(Vec(partWayNum, DecoupledIO(new ICacheReadBundle)))
27+
val readResp: ICacheDataRespBundle = Output(new ICacheDataRespBundle)
28+
}
29+
30+
val io: ICacheDataArrayIO = IO(new ICacheDataArrayIO)
31+
3032
class ICacheDataEntry(implicit p: Parameters) extends ICacheBundle {
3133
val data: UInt = UInt(ICacheDataBits.W)
3234
val code: UInt = UInt(ICacheDataCodeBits.W)
@@ -41,8 +43,6 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheModule with ICacheEC
4143
}
4244
}
4345

44-
val io: ICacheDataArrayIO = IO(new ICacheDataArrayIO)
45-
4646
/**
4747
******************************************************************************
4848
* data array

‎src/main/scala/xiangshan/frontend/icache/ICacheImp.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ import xiangshan.cache.mmu.TlbRequestIO
3636
import xiangshan.frontend.FtqToPrefetchIO
3737

3838
class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents {
39-
4039
class ICacheIO(implicit p: Parameters) extends ICacheBundle {
4140
val hartId: UInt = Input(UInt(hartIdLen.W))
4241
// FTQ
@@ -64,6 +63,7 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
6463
// perf
6564
val perfInfo: ICachePerfInfo = Output(new ICachePerfInfo)
6665
}
66+
6767
val io: ICacheIO = IO(new ICacheIO)
6868

6969
println("ICache:")
@@ -86,7 +86,7 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
8686
private val mainPipe = Module(new ICacheMainPipe)
8787
private val missUnit = Module(new ICacheMissUnit(edge))
8888
private val replacer = Module(new ICacheReplacer)
89-
private val prefetcher = Module(new IPrefetchPipe)
89+
private val prefetcher = Module(new ICachePrefetchPipe)
9090
private val wayLookup = Module(new WayLookup)
9191

9292
private val ecc_enable = if (outer.ctrlUnitOpt.nonEmpty) outer.ctrlUnitOpt.get.module.io.ecc_enable else true.B

‎src/main/scala/xiangshan/frontend/icache/ICacheMSHR.scala

+1
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ class ICacheMSHR(edge: TLEdgeOut, isFetch: Boolean, ID: Int)(implicit p: Paramet
3333
val resp: Valid[MSHRResp] = ValidIO(new MSHRResp)
3434
val victimWay: UInt = Input(UInt(wayBits.W))
3535
}
36+
3637
val io: ICacheMSHRIO = IO(new ICacheMSHRIO(edge))
3738

3839
private val valid = RegInit(Bool(), false.B)

‎src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala

+27-33
Original file line numberDiff line numberDiff line change
@@ -30,44 +30,38 @@ import xiangshan.cache.mmu.TlbCmd
3030
import xiangshan.cache.mmu.ValidHoldBypass // FIXME: should move this to utility?
3131
import xiangshan.frontend.ExceptionType
3232

33-
class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle {
34-
val hartId: UInt = Input(UInt(hartIdLen.W))
35-
36-
/*** internal interface ***/
37-
val dataArray: ICacheDataReqBundle = new ICacheDataReqBundle
38-
val metaArrayFlush: Vec[Valid[ICacheMetaFlushBundle]] = Vec(PortNumber, ValidIO(new ICacheMetaFlushBundle))
39-
val touch: Vec[Valid[ReplacerTouch]] = Vec(PortNumber, ValidIO(new ReplacerTouch))
40-
val wayLookupRead: DecoupledIO[WayLookupInfo] = Flipped(DecoupledIO(new WayLookupInfo))
41-
val mshr: ICacheMSHRBundle = new ICacheMSHRBundle
42-
val ecc_enable: Bool = Input(Bool())
43-
44-
/*** outside interface ***/
45-
// FTQ
46-
val fetch: ICacheMainPipeBundle = new ICacheMainPipeBundle
47-
val flush: Bool = Input(Bool())
48-
// PMP
49-
val pmp: Vec[ICachePMPBundle] = Vec(PortNumber, new ICachePMPBundle)
50-
// IFU
51-
val respStall: Bool = Input(Bool())
52-
// backend/BEU
53-
val errors: Vec[Valid[L1CacheErrorInfo]] = Output(Vec(PortNumber, ValidIO(new L1CacheErrorInfo)))
54-
55-
/*** PERF ***/
56-
val perfInfo: ICachePerfInfo = Output(new ICachePerfInfo)
57-
}
58-
59-
//class ICacheDB(implicit p: Parameters) extends ICacheBundle {
60-
// val blk_vaddr: UInt = UInt((VAddrBits - blockOffBits).W)
61-
// val blk_paddr: UInt = UInt((PAddrBits - blockOffBits).W)
62-
// val hit: Bool = Bool()
63-
//}
64-
6533
class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
6634
with ICacheECCHelper
6735
with ICacheAddrHelper
6836
with ICacheDataSelHelper {
6937

70-
val io: ICacheMainPipeInterface = IO(new ICacheMainPipeInterface)
38+
class ICacheMainPipeIO(implicit p: Parameters) extends ICacheBundle {
39+
val hartId: UInt = Input(UInt(hartIdLen.W))
40+
41+
/*** internal interface ***/
42+
val dataArray: ICacheDataReqBundle = new ICacheDataReqBundle
43+
val metaArrayFlush: Vec[Valid[ICacheMetaFlushBundle]] = Vec(PortNumber, ValidIO(new ICacheMetaFlushBundle))
44+
val touch: Vec[Valid[ReplacerTouch]] = Vec(PortNumber, ValidIO(new ReplacerTouch))
45+
val wayLookupRead: DecoupledIO[WayLookupInfo] = Flipped(DecoupledIO(new WayLookupInfo))
46+
val mshr: ICacheMSHRBundle = new ICacheMSHRBundle
47+
val ecc_enable: Bool = Input(Bool())
48+
49+
/*** outside interface ***/
50+
// FTQ
51+
val fetch: ICacheMainPipeBundle = new ICacheMainPipeBundle
52+
val flush: Bool = Input(Bool())
53+
// PMP
54+
val pmp: Vec[ICachePMPBundle] = Vec(PortNumber, new ICachePMPBundle)
55+
// IFU
56+
val respStall: Bool = Input(Bool())
57+
// backend/BEU
58+
val errors: Vec[Valid[L1CacheErrorInfo]] = Output(Vec(PortNumber, ValidIO(new L1CacheErrorInfo)))
59+
60+
/*** PERF ***/
61+
val perfInfo: ICachePerfInfo = Output(new ICachePerfInfo)
62+
}
63+
64+
val io: ICacheMainPipeIO = IO(new ICacheMainPipeIO)
7165

7266
/** Input/Output port */
7367
private val (fromFtq, toIFU) = (io.fetch.req, io.fetch.resp)

‎src/main/scala/xiangshan/frontend/icache/ICacheMetaArray.scala

+10-10
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,17 @@ import utility.XSPerfAccumulate
2222
import utility.mbist.MbistPipeline
2323
import utility.sram.SRAMTemplate
2424

25-
class ICacheMetaArrayIO(implicit p: Parameters) extends ICacheBundle {
26-
val write: DecoupledIO[ICacheMetaWriteBundle] = Flipped(DecoupledIO(new ICacheMetaWriteBundle))
27-
val read: DecoupledIO[ICacheReadBundle] = Flipped(DecoupledIO(new ICacheReadBundle))
28-
val readResp: ICacheMetaRespBundle = Output(new ICacheMetaRespBundle)
29-
val flush: Vec[Valid[ICacheMetaFlushBundle]] = Vec(PortNumber, Flipped(ValidIO(new ICacheMetaFlushBundle)))
30-
val flushAll: Bool = Input(Bool())
31-
}
32-
3325
class ICacheMetaArray(implicit p: Parameters) extends ICacheModule with ICacheECCHelper {
26+
class ICacheMetaArrayIO(implicit p: Parameters) extends ICacheBundle {
27+
val write: DecoupledIO[ICacheMetaWriteBundle] = Flipped(DecoupledIO(new ICacheMetaWriteBundle))
28+
val read: DecoupledIO[ICacheReadBundle] = Flipped(DecoupledIO(new ICacheReadBundle))
29+
val readResp: ICacheMetaRespBundle = Output(new ICacheMetaRespBundle)
30+
val flush: Vec[Valid[ICacheMetaFlushBundle]] = Vec(PortNumber, Flipped(ValidIO(new ICacheMetaFlushBundle)))
31+
val flushAll: Bool = Input(Bool())
32+
}
33+
34+
val io: ICacheMetaArrayIO = IO(new ICacheMetaArrayIO)
35+
3436
class ICacheMetaEntry(implicit p: Parameters) extends ICacheBundle {
3537
val meta: ICacheMetadata = new ICacheMetadata
3638
val code: UInt = UInt(ICacheMetaCodeBits.W)
@@ -48,8 +50,6 @@ class ICacheMetaArray(implicit p: Parameters) extends ICacheModule with ICacheEC
4850
// sanity check
4951
require(ICacheMetaEntryBits == (new ICacheMetaEntry).getWidth)
5052

51-
val io: ICacheMetaArrayIO = IO(new ICacheMetaArrayIO)
52-
5353
private val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0)
5454
private val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0)
5555
private val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine

‎src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala

+21-21
Original file line numberDiff line numberDiff line change
@@ -28,28 +28,28 @@ import utility.Constantin
2828
import utility.XSPerfAccumulate
2929
import xiangshan.XSCoreParamsKey
3030

31-
class ICacheMissUnitIO(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheBundle {
32-
// difftest
33-
val hartId: Bool = Input(Bool())
34-
// control
35-
val fencei: Bool = Input(Bool())
36-
val flush: Bool = Input(Bool())
37-
// fetch
38-
val fetch_req: DecoupledIO[ICacheMissReq] = Flipped(DecoupledIO(new ICacheMissReq))
39-
val fetch_resp: Valid[ICacheMissResp] = ValidIO(new ICacheMissResp)
40-
// prefetch
41-
val prefetch_req: DecoupledIO[ICacheMissReq] = Flipped(DecoupledIO(new ICacheMissReq))
42-
// SRAM Write Req
43-
val meta_write: DecoupledIO[ICacheMetaWriteBundle] = DecoupledIO(new ICacheMetaWriteBundle)
44-
val data_write: DecoupledIO[ICacheDataWriteBundle] = DecoupledIO(new ICacheDataWriteBundle)
45-
// get victim from replacer
46-
val victim: ReplacerVictim = new ReplacerVictim
47-
// Tilelink
48-
val mem_acquire: DecoupledIO[TLBundleA] = DecoupledIO(new TLBundleA(edge.bundle))
49-
val mem_grant: DecoupledIO[TLBundleD] = Flipped(DecoupledIO(new TLBundleD(edge.bundle)))
50-
}
51-
5231
class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheModule with ICacheAddrHelper {
32+
class ICacheMissUnitIO(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheBundle {
33+
// difftest
34+
val hartId: Bool = Input(Bool())
35+
// control
36+
val fencei: Bool = Input(Bool())
37+
val flush: Bool = Input(Bool())
38+
// fetch
39+
val fetch_req: DecoupledIO[ICacheMissReq] = Flipped(DecoupledIO(new ICacheMissReq))
40+
val fetch_resp: Valid[ICacheMissResp] = ValidIO(new ICacheMissResp)
41+
// prefetch
42+
val prefetch_req: DecoupledIO[ICacheMissReq] = Flipped(DecoupledIO(new ICacheMissReq))
43+
// SRAM Write Req
44+
val meta_write: DecoupledIO[ICacheMetaWriteBundle] = DecoupledIO(new ICacheMetaWriteBundle)
45+
val data_write: DecoupledIO[ICacheDataWriteBundle] = DecoupledIO(new ICacheDataWriteBundle)
46+
// get victim from replacer
47+
val victim: ReplacerVictim = new ReplacerVictim
48+
// Tilelink
49+
val mem_acquire: DecoupledIO[TLBundleA] = DecoupledIO(new TLBundleA(edge.bundle))
50+
val mem_grant: DecoupledIO[TLBundleD] = Flipped(DecoupledIO(new TLBundleD(edge.bundle)))
51+
}
52+
5353
val io: ICacheMissUnitIO = IO(new ICacheMissUnitIO(edge))
5454

5555
/**

‎src/main/scala/xiangshan/frontend/icache/IPrefetch.scala ‎src/main/scala/xiangshan/frontend/icache/ICachePrefetchPipe.scala

+19-19
Original file line numberDiff line numberDiff line change
@@ -29,28 +29,28 @@ import xiangshan.cache.mmu.ValidHoldBypass // FIXME: should move this to utility
2929
import xiangshan.frontend.BpuFlushInfo
3030
import xiangshan.frontend.ExceptionType
3131

32-
class IPrefetchIO(implicit p: Parameters) extends ICacheBundle {
33-
// control
34-
val csr_pf_enable: Bool = Input(Bool())
35-
val ecc_enable: Bool = Input(Bool())
36-
val flush: Bool = Input(Bool())
37-
38-
val req: DecoupledIO[IPrefetchReq] = Flipped(Decoupled(new IPrefetchReq))
39-
val flushFromBpu: BpuFlushInfo = Flipped(new BpuFlushInfo)
40-
val itlb: Vec[TlbRequestIO] = Vec(PortNumber, new TlbRequestIO)
41-
val itlbFlushPipe: Bool = Bool()
42-
val pmp: Vec[ICachePMPBundle] = Vec(PortNumber, new ICachePMPBundle)
43-
val metaRead: ICacheMetaReqBundle = new ICacheMetaReqBundle
44-
val MSHRReq: DecoupledIO[ICacheMissReq] = DecoupledIO(new ICacheMissReq)
45-
val MSHRResp: Valid[ICacheMissResp] = Flipped(ValidIO(new ICacheMissResp))
46-
val wayLookupWrite: DecoupledIO[WayLookupInfo] = DecoupledIO(new WayLookupInfo)
47-
}
48-
49-
class IPrefetchPipe(implicit p: Parameters) extends ICacheModule
32+
class ICachePrefetchPipe(implicit p: Parameters) extends ICacheModule
5033
with ICacheECCHelper
5134
with ICacheAddrHelper {
5235

53-
val io: IPrefetchIO = IO(new IPrefetchIO)
36+
class ICachePrefetchPipeIO(implicit p: Parameters) extends ICacheBundle {
37+
// control
38+
val csr_pf_enable: Bool = Input(Bool())
39+
val ecc_enable: Bool = Input(Bool())
40+
val flush: Bool = Input(Bool())
41+
42+
val req: DecoupledIO[IPrefetchReq] = Flipped(Decoupled(new IPrefetchReq))
43+
val flushFromBpu: BpuFlushInfo = Flipped(new BpuFlushInfo)
44+
val itlb: Vec[TlbRequestIO] = Vec(PortNumber, new TlbRequestIO)
45+
val itlbFlushPipe: Bool = Bool()
46+
val pmp: Vec[ICachePMPBundle] = Vec(PortNumber, new ICachePMPBundle)
47+
val metaRead: ICacheMetaReqBundle = new ICacheMetaReqBundle
48+
val MSHRReq: DecoupledIO[ICacheMissReq] = DecoupledIO(new ICacheMissReq)
49+
val MSHRResp: Valid[ICacheMissResp] = Flipped(ValidIO(new ICacheMissResp))
50+
val wayLookupWrite: DecoupledIO[WayLookupInfo] = DecoupledIO(new WayLookupInfo)
51+
}
52+
53+
val io: ICachePrefetchPipeIO = IO(new ICachePrefetchPipeIO)
5454

5555
private val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp))
5656
private val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp))

‎src/main/scala/xiangshan/frontend/icache/WayLookup.scala

+8-8
Original file line numberDiff line numberDiff line change
@@ -21,18 +21,18 @@ import org.chipsalliance.cde.config.Parameters
2121
import utility.CircularQueuePtr
2222
import xiangshan.frontend.ExceptionType
2323

24-
class WayLookupInterface(implicit p: Parameters) extends ICacheBundle {
25-
val flush: Bool = Input(Bool())
26-
val read: DecoupledIO[WayLookupInfo] = DecoupledIO(new WayLookupInfo)
27-
val write: DecoupledIO[WayLookupInfo] = Flipped(DecoupledIO(new WayLookupInfo))
28-
val update: Valid[ICacheMissResp] = Flipped(ValidIO(new ICacheMissResp))
29-
}
30-
3124
class WayLookup(implicit p: Parameters) extends ICacheModule
3225
with ICacheECCHelper
3326
with ICacheAddrHelper {
3427

35-
val io: WayLookupInterface = IO(new WayLookupInterface)
28+
class WayLookupIO(implicit p: Parameters) extends ICacheBundle {
29+
val flush: Bool = Input(Bool())
30+
val read: DecoupledIO[WayLookupInfo] = DecoupledIO(new WayLookupInfo)
31+
val write: DecoupledIO[WayLookupInfo] = Flipped(DecoupledIO(new WayLookupInfo))
32+
val update: Valid[ICacheMissResp] = Flipped(ValidIO(new ICacheMissResp))
33+
}
34+
35+
val io: WayLookupIO = IO(new WayLookupIO)
3636

3737
class WayLookupPtr extends CircularQueuePtr[WayLookupPtr](nWayLookupSize)
3838
private object WayLookupPtr {

0 commit comments

Comments
 (0)