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fix(csr): CSRR instruction read xireg inOrder #10539

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fix(csr): CSRR instruction read xireg inOrder

fix(csr): CSRR instruction read xireg inOrder #10539

Triggered via pull request March 11, 2025 06:39
@sinceforYysinceforYy
synchronize #4393
fix-csrr
Status Failure
Total duration 5m 30s
Artifacts –

emu.yml

on: pull_request
Changes Detection
4s
Changes Detection
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1m 50s
Generate Verilog
EMU - Basics
1m 49s
EMU - Basics
EMU - CHI
1m 48s
EMU - CHI
EMU - Performance
1m 47s
EMU - Performance
EMU - MC
1m 50s
EMU - MC
SIMV - Basics
3m 14s
SIMV - Basics
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3m 28s
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Check Submodules
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7 errors and 1 warning
EMU - Performance
Process completed with exit code 2.
EMU - CHI
Process completed with exit code 2.
EMU - Basics
Process completed with exit code 2.
EMU - MC
Process completed with exit code 2.
Generate Verilog
Process completed with exit code 2.
SIMV - Basics
Process completed with exit code 2.
Upload Artifacts
Process completed with exit code 2.
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']