fix(csr): CSRR instruction read xireg inOrder

[sinceforYy]

• AIA registers are designed to be access asynchronously, so newCSR will wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg inOrder.

[XiangShanRobot]

[Generated by IPC robot]
commit: 2fdfd33

commit	astar	copy_and_run	coremark	gcc	gromacs	hmmer-Vector	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
2fdfd33	1.806	0.442	2.641	1.226	2.150	1.676	2.149	2.364	0.933	1.389	2.010	3.108	2.538	2.274	3.309

master branch:

commit	astar	copy_and_run	coremark	gcc	gromacs	hmmer-Vector	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
42b75a5	1.806	0.442	2.641	1.229	2.150	1.676	2.149	2.364	0.933	1.378	2.010	3.108	2.538	2.274	3.309
f9395f7	1.806	0.442	2.641	1.229	2.150	1.676	2.149	2.364	0.933	1.389	2.010	3.108	2.538	2.274	3.309
c1eb288	1.806	0.442	2.641	1.237	2.150	1.676	2.149	2.364	0.933	1.389	2.010	3.108	2.538	2.274	3.309
9d7a35d	1.822	0.442	2.641	1.228	2.158	1.676	2.144	2.364	0.940	1.378	1.972	3.112	2.538	2.272	3.300
fad7c42	1.823	0.442	2.641	1.228	2.158	1.676	2.144	2.364	0.940	1.389	1.972	3.112	2.538	2.272	3.300
dfb03ba	1.822	0.442	2.641	1.234	2.158	1.676	2.144	2.364	0.940	1.378	1.972	3.112	2.538	2.272	3.300
d6b0a27	1.823	0.442	2.641	1.226	2.158	1.676	2.144	2.364	0.940	1.378	1.972	3.112	2.538	2.272	3.300
591ae1c	1.822	0.442	2.641	1.236	2.158	1.676	2.144	2.364	0.940	1.389	1.972	3.112	2.538	2.272	3.300
11269ca	1.823	0.442	2.641	1.231	2.158	1.676	2.144	2.364	0.940	1.389	1.972	3.112	2.538	2.272	3.300
7fbc1cb	1.823	0.442	2.641	1.233	2.158	1.676	2.144	2.364	0.940	1.378	1.972	3.112	2.538	2.272	3.300