Update Notice.md #1

hsibert · 2014-06-12T14:07:01Z

Added some precisions on license terms in notice.md

Update Notice.md

Build information includes: - Version string as returned by 'git describe --dirty' - Build counter (#1 initially or after 'make clean') - Build date - Link format For example: 0.2.0-107-g4d0acfc #1 Tue May 12 16:02:57 UTC 2015 elf32-littlearm Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

Build information includes: - Version string as returned by 'git describe --dirty' - Build counter (#1 initially or after 'make clean') - Build date/time - Linker architecture ('arm', 'aarch64') For example: 0.2.0-107-g985d7d8 #1 Tue May 12 16:49:14 UTC 2015 aarch64 Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

Build information includes: - Version string as returned by 'git describe --always --dirty' - Build counter (#1 initially or after 'make clean') - Build date/time - Linker architecture ('arm', 'aarch64') For example: 0.2.0-107-g985d7d8 #1 Tue May 12 16:49:14 UTC 2015 aarch64 Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

Build information includes: - Version string as returned by 'git describe --always --dirty' - Build counter (#1 initially or after 'make clean') - Build date/time - Linker architecture ('arm', 'aarch64') For example: 0.2.0-107-g985d7d8 #1 Tue May 12 16:49:14 UTC 2015 aarch64 Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

There is a race condition in the code that creates and deletes trusted storage. If multiple threads invoke a multi-session TA to create and delete different files (such as xtest 6016), the following can occur: Thread #1 (create file #1) | Thread #2 (delete file #2) | | remove("/TA_dir/file"); mkdir("/TA_dir"); | | rmdir("/TA_dir"); create("/TA_dir/file1"); | => ENOENT | Add a mutex to prevent this race condition. Note: the bug is currently not triggered by xtest 1016 because the test is run for RPMB FS only, and because directory operations are no-ops in the RPMB implementation. The fix will be needed when enabling single-TA concurrency with the REE and SQL backends. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

There is a race condition in the code that creates and deletes trusted storage. If multiple threads invoke a multi-session TA to create and delete different files (such as xtest 6016), the following can occur: Thread #1 (create file #1) | Thread #2 (delete file #2) | | unlink("/TA_dir/file2"); mkdir("/TA_dir"); | | rmdir("/TA_dir"); create("/TA_dir/file1"); | => ENOENT | Add a mutex to prevent this race condition. Note: the bug is currently not triggered by xtest 1016 because the test is run for RPMB FS only, and because directory operations are no-ops in the RPMB implementation. The fix will be needed when enabling single-TA concurrency with the REE and SQL backends. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

The first and and fourth lines in the boot sequence below are debug messages that should not be printed when the log level is INFO: INFO: TEE-CORE: No NSEC DDR memory area defined INFO: TEE-CORE: INFO: TEE-CORE: OP-TEE version: 2.5.0-rc1 #1 Wed Jun 28 15:11:06 UTC 2017 aarch64 INFO: TEE-CORE: Shared memory address range: 3dc00000, 3f000000 INFO: TEE-CORE: Initialized Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

The first and and fourth lines in the boot sequence below are debug messages that should not be printed when the log level is INFO: INFO: TEE-CORE: No NSEC DDR memory area defined INFO: TEE-CORE: INFO: TEE-CORE: OP-TEE version: 2.5.0-rc1 #1 Wed Jun 28 15:11:06 UTC 2017 aarch64 INFO: TEE-CORE: Shared memory address range: 3dc00000, 3f000000 INFO: TEE-CORE: Initialized Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr fuse: [OK] I/TC: ---- rd usr fuse: [OK] I/TC: ---- rd dna fuse: [OK] I/TC: ---- rd ppk fuse: [OK] I/TC: ---- rd iv fuse: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> done

When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] I/TC: ---- rd puf ctrl: [OK] I/TC: ---- rd puf: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

Current: - TRNG (random number generation) - PM: soc version, FPGA programming - FPGA needs the buffer in DDR - MBOX (PLM comms with different services) - NVM (interface to the efuse service) - crypto: ECC, RSA, HASH, AES-GCM When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] I/TC: ---- rd puf ctrl: [OK] I/TC: ---- rd puf: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

Current: - TRNG (random number generation) - PM: soc version, FPGA programming - FPGA needs the buffer in DDR - MBOX (PLM comms with different services) - NVM (interface to the efuse service) - PUF (interface to the puf service) - policy missing. - crypto: ECC, RSA, HASH, AES-GCM When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] I/TC: ---- rd puf ctrl: [OK] I/TC: ---- rd puf: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

Current: - TRNG (random number generation) - PM: soc version, FPGA programming - FPGA needs the buffer in DDR - MBOX (PLM comms with different services) - NVM (interface to the efuse service) - PUF (interface to the puf service) - policy missing. - crypto: ECC, RSA, HASH, AES-GCM When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] I/TC: ---- rd puf ctrl: [OK] I/TC: ---- rd puf: [OK] I/TC: Versal: Test PUF I/TC: ---- api: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

Current: - TRNG (random number generation) - PM: soc version, FPGA programming - FPGA needs the buffer in DDR - MBOX (PLM comms with different services) - NVM (interface to the efuse service) - PUF (interface to the puf service) - policy missing. - crypto: ECC, RSA, HASH, AES-GCM - gpio: added Zynq driver but only functional on Versal When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] I/TC: ---- rd puf ctrl: [OK] I/TC: ---- rd puf: [OK] I/TC: Versal: Test PUF I/TC: ---- api: [OK] D/TC:0 0 call_initcalls:40 level 5 versal_gpio_test() I/TC: Versal: Test GPIO I/TC: ---- poll out: [OK] I/TC: ---- poll inp: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

Plat-imx: Add i.MX6Q VAB-820 Board config

…uild Fix an issue with the build number in the version string. While at it, factor out the duplicated code into mk/macros.mk. Before: $ rm -rf out/ $ make out/arm-plat-vexpress/core/version.o UPD out/arm-plat-vexpress/core/.buildcount GEN out/arm-plat-vexpress/core/version.o cat: out/arm-plat-vexpress/core/.buildcount: No such file or directory In addition to the error message, note the missing build number after the hash sign: $ strings out/arm-plat-vexpress/core/version.o | grep UTC 4.3.0-48-g9c97e7d52 (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) # Wed Aug 14 16:17:07 UTC 2024 arm After: $ rm -rf out/ $ make out/arm-plat-vexpress/core/version.o UPD out/arm-plat-vexpress/core/.buildcount GEN out/arm-plat-vexpress/core/version.o $ strings out/arm-plat-vexpress/core/version.o | grep UTC 4.3.0-48-g9c97e7d52-dev (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) #1 Wed Aug 14 16:17:24 UTC 2024 arm Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

…uild Fix an issue with the build number in the version string. While at it, factor out the duplicated code into mk/macros.mk. Before: $ rm -rf out/ $ make out/arm-plat-vexpress/core/version.o UPD out/arm-plat-vexpress/core/.buildcount GEN out/arm-plat-vexpress/core/version.o cat: out/arm-plat-vexpress/core/.buildcount: No such file or directory In addition to the error message, note the missing build number after the hash sign: $ strings out/arm-plat-vexpress/core/version.o | grep UTC 4.3.0-48-g9c97e7d52 (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) # Wed Aug 14 16:17:07 UTC 2024 arm After: $ rm -rf out/ $ make out/arm-plat-vexpress/core/version.o UPD out/arm-plat-vexpress/core/.buildcount GEN out/arm-plat-vexpress/core/version.o $ strings out/arm-plat-vexpress/core/version.o | grep UTC 4.3.0-48-g9c97e7d52-dev (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) OP-TEE#1 Wed Aug 14 16:17:24 UTC 2024 arm Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Update Notice.md

3b2457a

ghost pushed a commit that referenced this pull request Jun 12, 2014

Merge pull request #1 from hsibert/patch-1

7c6ae17

Update Notice.md

ghost merged commit 7c6ae17 into OP-TEE:master Jun 12, 2014

jforissier mentioned this pull request May 13, 2015

core: log build information on init #300

Merged

sakjain92 mentioned this pull request Jul 1, 2015

Kernel Panic - OPTEE on Arm Foundation Model #373

Closed

ardbiesheuvel referenced this pull request in jforissier/optee_os Jul 7, 2015

[Review] Simplify exit of ce_aes_xts_encrypt() and ce_aes_xts_decrypt()

d1057ae

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

neil1899 mentioned this pull request Oct 20, 2015

tee-supplicant panic & ta panic #506

Closed

neil1899 mentioned this pull request Dec 8, 2015

concurrent ta #577

Closed

targetnull mentioned this pull request Apr 2, 2016

No optee.ko in linux/drivers/tee/optee. #727

Closed

targetnull mentioned this pull request Apr 17, 2016

How to access sharedmemory from kernel space? #742

Closed

louisyang1977 mentioned this pull request Aug 1, 2016

Is it possible to use NEON at TA ?? #953

Closed

etienne-lms mentioned this pull request Sep 29, 2016

bad mapping of TA secure memref parameters #1081

Closed

acy54321 mentioned this pull request Oct 26, 2016

32bit OPTEE OS System call interface Question #1139

Closed

suihkulokki mentioned this pull request Nov 29, 2016

xtest fails on hikey #1202

Closed

xfeng12 mentioned this pull request Mar 11, 2017

Kernel panic with CAAM on IMX6UL EVK? #1408

Closed

This was referenced Mar 15, 2017

communication to hikey via network problems #1392

Closed

hikey_debian: tee-supplicant fails: please clarify the build instruction around tee-supplicant, xtest #1432

Closed

deepakmnvl mentioned this pull request May 18, 2017

TA compilation with SPI driver #1461

Closed

jforissier mentioned this pull request Jun 28, 2017

core: demote a couple of messages from IMSG() to DMSG() #1645

Merged

AllenSiao mentioned this pull request Aug 22, 2017

user TA got read permission fault #1763

Closed

lorc mentioned this pull request Oct 10, 2017

TA from older version crashes stack unwind layer in OP-TEE (WAS Stack unwind causes data abort on Rcar M3 board) #1872

Closed

maroonmoon13 mentioned this pull request Aug 8, 2022

Optee panics on AM64x-starter kit #5461

Closed

weizhaojiang mentioned this pull request Nov 3, 2022

core: implement a method to dump user ta's runtime status. #5590

Closed

zzbios mentioned this pull request Nov 27, 2022

In the case that SEL2(SPMC) is enabled, when hafnium execute the vcpu_restore_all_and_run, below errors occured #5674

Closed

CyanDevs pushed a commit to CyanDevs/optee_os that referenced this pull request Jan 23, 2023

Merge pull request OP-TEE#1 from ShiaujiuanChen/ms-iot

89f683b

Plat-imx: Add i.MX6Q VAB-820 Board config

guagua-m mentioned this pull request May 25, 2023

Installing a key on secure storage #6046

Closed

ZhanYF mentioned this pull request Feb 10, 2024

Measured boot on rk3399: Failed to map TPM log memory #6679

Closed

ydonghyuk mentioned this pull request Feb 21, 2024

Question about panic of TA2 in TA1-TA2 connection. #6701

Closed

sungkeunsong mentioned this pull request Jun 15, 2024

CSD locking issue #6893

Closed

ldshyu mentioned this pull request Jun 28, 2024

core: arm64: Fixing SHA3-224 failed when using ARMv8.2-A cryptographic extensions #6920

Merged

GlovePuppet mentioned this pull request Sep 16, 2024

Getting stuck in wait_for_completion_interruptible #7042

Closed

yuvraj1803 mentioned this pull request Dec 16, 2024

OPTEE assertion fail in bpool when OPTEE_SMC_VM_CREATED is called a second time #7182

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markz-zhang mentioned this pull request Feb 12, 2025

The 1GB VA constraint #7275

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Update Notice.md #1

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hsibert commented Jun 12, 2014

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hsibert commented Jun 12, 2014