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drivers: versal: drivers to upstream [WIP]
Current: - TRNG (random number generation) - PM: soc version, FPGA programming - FPGA needs the buffer in DDR - MBOX (PLM comms with different services) - NVM (interface to the efuse service) - crypto: ECC, RSA, HASH, AES-GCM When booting this OP-TEE, the tests get executed This is the expected output. OP-TEE build flags: make -j 8 PLATFORM=versal \ CFG_TEE_CORE_LOG_LEVEL=4 \ CFG_VERSAL_TRACE_PLM=y \ CFG_VERSAL_CRYPTO_DRIVER=y \ CFG_CRYPTO_DRIVER_DEBUG=y \ CFG_EARLY_TA=y \ CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \ -C /home/jramirez/Work/xilinx/project/local,optee-os \ O=/home/jramirez/Work/xilinx/project/.build/op-tee OP-TEE output: I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64 I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init() D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000 D/TC:0 0 call_initcalls:40 level 1 register_time_source() D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init() D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram() D/TC:0 0 call_initcalls:40 level 3 platform_banner() I/TC: Platform Versal - Silicon Revision v2 D/TC:0 0 call_initcalls:40 level 3 check_ta_store() D/TC:0 0 check_ta_store:408 TA store: "early TA" D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA" D/TC:0 0 check_ta_store:408 TA store: "REE" D/TC:0 0 call_initcalls:40 level 3 early_ta_init() D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616) D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance() D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init() D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager() D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init() D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test() I/TC: Versal: Test NVM I/TC: ---- wr usr: [OK] I/TC: ---- rd usr: [OK] I/TC: ---- rd dna: [OK] I/TC: ---- rd ppk: [OK] I/TC: ---- rd iv: [OK] I/TC: ---- rd rvk: [OK] I/TC: ---- rd misc: [OK] I/TC: ---- rd sec ctrl: [OK] I/TC: ---- rd sec misc: [OK] I/TC: ---- rd boot env: [OK] I/TC: ---- rd off rvk: [OK] I/TC: ---- rd dec only: [OK] I/TC: ---- rd puf ctrl: [OK] I/TC: ---- rd puf: [OK] D/TC:0 0 call_initcalls:40 level 5 ecc_init() D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348 D/TC:0 0 call_initcalls:40 level 5 rsa_init() D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0 D/TC:0 0 call_initcalls:40 level 5 sha3_init() D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test() D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0 D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0 D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0 D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0 I/TC: Versal: Test ECC I/TC: ---- ecc gen pair: [OK] I/TC: ---- ecc gen sign: [OK] I/TC: ---- ecc ver sign: [OK] D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc() D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460 D/TC:0 0 call_initcalls:40 level 6 mobj_init() D/TC:0 0 call_initcalls:40 level 6 default_mobj_init() D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test() D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0 D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0 D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free I/TC: Versal: Test RSA I/TC: ---- rsa decrypt: [OK] I/TC: ---- rsa encrypt: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test() D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005 D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0 I/TC: Versal: Test HASH I/TC: ---- hash sha384: [OK] D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test() D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810 D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_enc_final:231 authenc ret 0x0 D/TC:0 0 authenc_init:107 authenc ret 0x0 D/TC:0 0 authenc_update_aad:139 authenc ret 0x0 D/TC:0 0 authenc_dec_final:277 authenc ret 0x0 I/TC: Versal: Test AUTHENC I/TC: ---- auth enc: [OK] I/TC: ---- auth dec: [OK] I/TC: Primary CPU switching to normal world boot INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x8000000 INFO: SPSR = 0x3c9 U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200) Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
1 parent 3f957d1 commit 71cd3b2

25 files changed

+5052
-1
lines changed

‎core/arch/arm/plat-versal/conf.mk

+20
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,23 @@ $(call force,CFG_WITH_LPAE,y)
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else
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$(call force,CFG_ARM32_core,y)
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endif
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$(call force, CFG_VERSAL_RNG_DRV, y)
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$(call force, CFG_WITH_SOFTWARE_PRNG,n)
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$(call force, CFG_VERSAL_PM, y)
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$(call force, CFG_VERSAL_MBOX, y)
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$(call force, CFG_VERSAL_NVM, y)
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# TRNG configuration
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CFG_VERSAL_TRNG_SEED_LIFE ?= 3
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CFG_VERSAL_TRNG_DF_MUL ?= 7
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# MBOX configuration
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CFG_VERSAL_MBOX_IPI_ID ?=3
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# Crypto
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CFG_VERSAL_CRYPTO_DRIVER ?= n
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# FPGA
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CFG_VERSAL_FPGA_INIT ?= n
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CFG_VERSAL_FPGA_DDR_ADDR ?= 0x80000

‎core/arch/arm/plat-versal/main.c

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@@ -7,6 +7,8 @@
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#include <console.h>
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#include <drivers/gic.h>
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#include <drivers/pl011.h>
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#include <drivers/versal_nvm.h>
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#include <drivers/versal_pm.h>
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#include <kernel/boot.h>
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#include <kernel/interrupt.h>
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#include <kernel/misc.h>
@@ -56,3 +58,28 @@ void console_init(void)
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CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
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register_serial_console(&console_data.chip);
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}
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static TEE_Result platform_banner(void)
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{
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TEE_Result ret = TEE_SUCCESS;
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uint8_t version = 0;
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ret = versal_soc_version(&version);
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if (ret) {
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EMSG("Failure to retrieve SoC version");
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return ret;
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}
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IMSG("Platform Versal - Silicon Revision v%d", version);
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if (IS_ENABLED(CFG_VERSAL_FPGA_INIT)) {
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ret = versal_write_fpga(CFG_VERSAL_FPGA_DDR_ADDR);
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if (ret) {
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EMSG("Failure to load the FPGA bitstream");
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return TEE_ERROR_GENERIC;
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}
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}
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return TEE_SUCCESS;
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}
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service_init(platform_banner);

‎core/arch/arm/plat-versal/platform_config.h

+5-1
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@@ -9,7 +9,8 @@
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#include <mm/generic_ram_layout.h>
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/* Make stacks aligned to data cache line length */
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#define STACK_ALIGNMENT 64
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#define CACHELINE_LEN 64
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#define STACK_ALIGNMENT CACHELINE_LEN
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#if defined(PLATFORM_FLAVOR_generic)
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@@ -29,6 +30,9 @@
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#define DRAM0_BASE 0
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#define DRAM0_SIZE 0x80000000
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#define TRNG_BASE 0xF1230000
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#define TRNG_SIZE 0x10000
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#ifdef ARM64
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/* DDR High area base is only available when compiling for 64 bits */
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#define DRAM1_BASE 0x800000000

‎core/drivers/crypto/sub.mk

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@@ -9,3 +9,5 @@ subdirs-$(CFG_NXP_SE05X) += se050
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subdirs-$(CFG_STM32_CRYPTO_DRIVER) += stm32
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subdirs-$(CFG_ASPEED_CRYPTO_DRIVER) += aspeed
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subdirs-$(CFG_VERSAL_CRYPTO_DRIVER) += versal

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