Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

New Architecture: Parallax Propeller #21559

Closed
ikskuh opened this issue Sep 30, 2024 · 4 comments · Fixed by #21563
Closed

New Architecture: Parallax Propeller #21559

ikskuh opened this issue Sep 30, 2024 · 4 comments · Fixed by #21563
Labels
contributor friendly This issue is limited in scope and/or knowledge of Zig internals. enhancement Solving this issue will likely involve adding new logic or components to the codebase.
Milestone

Comments

@ikskuh
Copy link
Contributor

ikskuh commented Sep 30, 2024

i'm planning to work on a project with the Parallax Propeller 2 and i didn't want to waste my time with C again.

I want to use the C backend to compile Zig to C and leverage existing compilers to work with Zig instead of C.

Can we add a propeller and propeller2 architecture with each having only a generic cpu with no cpu features?

Byte size is 8 bit, word/register size is 32 bit

The required address spaces are ram and cog for both architectures, and propeller2 has an additional lut address space.

Related: #7202

I'll try doing that myself when it's accepted to be done

@alexrp
Copy link
Member

alexrp commented Sep 30, 2024

Based on Andrew's previous comment here, I would suggest just going ahead with a PR. It doesn't seem to me like this would be controversial.

That said, a couple of questions:

  • What sets propeller2 apart from propeller that makes it worthwhile to have it be a separate Arch tag rather than modelling it with a CPU feature?
  • Has this architecture been used in the GNU ecosystem at all? If so, is there a precedent for what the architecture component of the triple should be called, and are we following it?

@ikskuh
Copy link
Contributor Author

ikskuh commented Sep 30, 2024

What sets propeller2 apart from propeller that makes it worthwhile to have it be a separate Arch tag rather than modelling it with a CPU feature?

Completely different ISA 🤣

Has this architecture been used in the GNU ecosystem at all? If so, is there a precedent for what the architecture component of the triple should be called, and are we following it?

https://www.parallax.com/propeller-2/programming-tools/

Not that i know of, but there's a LLVM port: https://github.com/ne75/p2llvm

@andrewrk andrewrk added enhancement Solving this issue will likely involve adding new logic or components to the codebase. contributor friendly This issue is limited in scope and/or knowledge of Zig internals. labels Sep 30, 2024
@andrewrk andrewrk added this to the unplanned milestone Sep 30, 2024
@andrewrk
Copy link
Member

Go for it 👍

@alexrp
Copy link
Member

alexrp commented Sep 30, 2024

FWIW, it doesn't seem like they're using a distinct propeller2 component. That's not to say that wouldn't make sense, just that it might be interesting to investigate why.

ikskuh pushed a commit to ikskuh/zig that referenced this issue Oct 1, 2024
These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores.

Resolves ziglang#21559
@andrewrk andrewrk modified the milestones: unplanned, 0.14.0 Oct 4, 2024
Ultra-Code pushed a commit to Ultra-Code/zig that referenced this issue Oct 8, 2024
* Adds new cpu architectures propeller1 and propeller2.

These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores.

Resolves ziglang#21559

* Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2
* Fixes missing switch prongs in src/codegen/llvm.zig
* Fixes order in std.Target.Arch

---------

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>
richerfu pushed a commit to richerfu/zig that referenced this issue Oct 28, 2024
* Adds new cpu architectures propeller1 and propeller2.

These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores.

Resolves ziglang#21559

* Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2
* Fixes missing switch prongs in src/codegen/llvm.zig
* Fixes order in std.Target.Arch

---------

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
contributor friendly This issue is limited in scope and/or knowledge of Zig internals. enhancement Solving this issue will likely involve adding new logic or components to the codebase.
Projects
None yet
Development

Successfully merging a pull request may close this issue.

3 participants