NVDLA Integration + Cleanup Ariane Preprocessing

.circleci/config.yml

@@ -262,6 +262,11 @@ jobs:
         steps:
             - prepare-rtl:
                 project-key: "testchipip"
+    prepare-chipyard-nvdla:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-nvdla"
     prepare-chipyard-spiflashwrite:
         executor: main-env
         steps:
@@ -368,6 +373,11 @@ jobs:
             - run-tests:
                 project-key: "chipyard-ariane"
                 timeout: "30m"
+    chipyard-nvdla-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "chipyard-nvdla"
     icenet-run-tests:
         executor: main-env
         steps:
@@ -484,6 +494,11 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
+            - prepare-chipyard-nvdla:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
             - prepare-chipyard-spiflashwrite:
                 requires:
                     - install-riscv-toolchain
@@ -567,6 +582,9 @@ workflows:
                 requires:
                     - prepare-chipyard-ariane
 
+            - chipyard-nvdla-run-tests:
+                requires:
+                    - prepare-chipyard-nvdla
             - icenet-run-tests:
                 requires:
                     - prepare-icenet

.circleci/defaults.sh

@@ -56,6 +56,7 @@ mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRo
 mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig"
 mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
 mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
+mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig"
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"

.circleci/run-tests.sh

@@ -80,6 +80,10 @@ case $1 in
     chipyard-ariane)
         make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
         ;;
+    chipyard-nvdla)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary
+        ;;
     icenet)
         make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]}
         ;;

.gitmodules

@@ -119,6 +119,12 @@
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git
+[submodule "generators/nvdla"]
+	path = generators/nvdla
+	url = https://github.com/ucb-bar/nvdla-wrapper.git
+[submodule "software/nvdla-workload"]
+	path = software/nvdla-workload
+	url = https://github.com/ucb-bar/nvdla-workload.git
 [submodule "tools/dromajo/dromajo-src"]
 	path = tools/dromajo/dromajo-src
 	url = https://github.com/abejgonzalez/dromajo.git

README.md

@@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -65,3 +65,4 @@ These publications cover many of the internal components used in Chipyard. Howev
 [firemarshal]: https://github.com/firesim/FireMarshal/
 [ariane]: https://github.com/pulp-platform/ariane/
 [gemmini]: https://github.com/ucb-bar/gemmini
+[nvdla]: http://nvdla.org/

build.sbt

@@ -129,7 +129,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/"))
 lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
-    gemmini, icenet, tracegen, ariane)
+    gemmini, icenet, tracegen, ariane, nvdla)
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
@@ -163,6 +163,10 @@ lazy val gemmini = (project in file("generators/gemmini"))
   .dependsOn(rocketchip, chisel_testers, testchipip)
   .settings(commonSettings)
 
+lazy val nvdla = (project in file("generators/nvdla"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
 lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
   .dependsOn(chisel_testers, chipyard)
   .settings(commonSettings)

common.mk

@@ -14,6 +14,7 @@ SHELL=/bin/bash
 #########################################################################################
 include $(base_dir)/generators/ariane/ariane.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
+include $(base_dir)/generators/nvdla/nvdla.mk
 include $(base_dir)/tools/dromajo/dromajo.mk
 
 #########################################################################################

docs/Generators/NVDLA.rst

@@ -0,0 +1,16 @@
+NVDLA
+====================================
+
+`NVDLA <http://nvdla.org/>`_ is an open-source deep learning accelerator developed by NVIDIA.
+The `NVDLA` is attached as a TileLink peripheral so it can be used as a component within the `Rocket Chip SoC generator`.
+The accelerator by itself exposes an AXI memory interface (or two if you use the "Large" configuration), a control interface, and an interrupt line.
+The main way to use the accelerator in Chipyard is to use the `NVDLA SW repository <https://github.com/ucb-bar/nvdla-sw>`_ that was ported to work on FireSim Linux.
+However, you can also use the accelerator in baremetal simulations (refer to ``tests/nvdla.c``).
+
+For more information on both the HW architecture and the SW, please visit their `website <http://nvdla.org/>`_.
+
+NVDLA Software with FireMarshal
+-------------------------------
+
+Located at ``software/nvdla-workload`` is a FireMarshal-based workload to boot Linux with the proper NVDLA drivers.
+Refer to that ``README.md`` for more information on how to run a simulation.

docs/Generators/index.rst

@@ -28,4 +28,5 @@ so changes to the generators themselves will automatically be used when building
    SiFive-Generators
    SHA3
    Ariane
+   NVDLA
 

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -72,7 +72,6 @@ class WithTracegenSystem extends Config((site, here, up) => {
   case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p))
 })
 
-
 class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => {
   case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) =>
     r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length))
@@ -83,12 +82,6 @@ class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here
   case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size)
 })
 
-
-
-// ------------------
-// Multi-RoCC Support
-// ------------------
-
 /**
  * Map from a hartId to a particular RoCC accelerator
  */

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -23,6 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
+  with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
 {
   override lazy val module = new DigitalTopModule(this)
 }

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -425,3 +425,41 @@ class RingSystemBusRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new freechips.rocketchip.system.BaseConfig)
 // DOC include end: RingSystemBusRocket
+
+class SmallNVDLARocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class LargeNVDLARocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -44,14 +44,12 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
   case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
 })
 
-
 class WithPerfCounters extends Config((site, here, up) => {
   case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
     core = tile.core.copy(nPerfCounters = 29)
   ))
 })
 
-
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
   case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
@@ -63,15 +61,16 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
   case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
 })
 
-
 // FASED Config Aliases. This to enable config generation via "_" concatenation
 // which requires that all config classes be defined in the same package
 class DDR3FRFCFS extends FRFCFS16GBQuadRank
 class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
 
 class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
 
-
+// Adds a small/large NVDLA to the system
+class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large")
+class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")
 
 
 // Tweaks that are generally applied to all firesim configs

scripts/insert-includes.py

@@ -0,0 +1,51 @@
+#!/usr/bin/python
+
+# replaces a `include with the full include file
+#
+# args
+# $1 - file to remove includes from
+# $2 - file to write output to
+# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs)
+#      includes are found relative to this path
+#      this is equivalent to something like +incdir+
+
+import sys
+import re
+import os
+
+inVlog = sys.argv[1]
+outVlog = sys.argv[2]
+print("[INFO] Replaces includes from: " + str(inVlog))
+
+if inVlog == outVlog:
+    sys.exit("[ERROR] The input and output file cannot be the same.")
+
+# add directories to search list
+incDirs = sys.argv[3:]
+print("[INFO] Searching following dirs for includes: " + str(incDirs))
+
+# open file
+with open(inVlog, 'r') as inFile:
+    with open(outVlog, 'w') as outFile:
+        # for each include found, search through all dirs and replace if found, error if not
+        for num, line in enumerate(inFile, 1):
+            match = re.match(r"^ *`include +\"(.*)\"", line)
+            if match:
+                # search for include and replace
+                found = False
+                for d in incDirs:
+                    potentialIncFileName = d + "/" + match.group(1)
+                    if os.path.exists(potentialIncFileName):
+                        found = True
+                        with open(potentialIncFileName, 'r') as incFile:
+                            for iline in incFile:
+                                outFile.write(iline)
+                        break
+
+                # must find something to include with
+                if not found:
+                    sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
+            else:
+                outFile.write(line)
+
+print("[INFO] Success. Writing output to: " + str(outVlog))

scripts/tutorial-patches/RocketConfigs.scala.patch

@@ -1,5 +1,5 @@
 diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-index 49d2238..afaa36d 100644
+index f29c580..0bd36ca 100644
 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
 +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
 @@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config(

scripts/tutorial-patches/build.sbt.patch

@@ -1,17 +1,17 @@
 diff --git a/build.sbt b/build.sbt
-index a633066..3df8b74 100644
+index 0c4581f..ff0597c 100644
 --- a/build.sbt
 +++ b/build.sbt
-@@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
+@@ -128,7 +128,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/"))
 
  lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
    .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
-     gemmini, icenet, tracegen, ariane)
+     gemmini, icenet, tracegen, ariane, nvdla)
    .settings(commonSettings)
 
-@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane"))
+@@ -155,9 +155,9 @@ lazy val ariane = (project in file("generators/ariane"))
    .dependsOn(rocketchip)
    .settings(commonSettings)
 

sims/vcs/Makefile

@@ -55,18 +55,16 @@ VCS_CC_OPTS = \
 
 VCS_NONCC_OPTS = \
 	+lint=all,noVCDE,noONGS,noUI \
-	-error=PCWM-L \
 	-timescale=1ns/1ps \
 	-quiet \
 	-q \
 	+rad \
-	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
 	-error=noZMMCM \
-	-assert svaext \
-	-sverilog \
-	+libext+.v \
+	-error=PCWM-L \
+	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	+incdir+$(build_dir) \
 	-f $(sim_common_files) \
 	$(sim_vsrcs)

sims/verilator/Makefile

@@ -72,7 +72,6 @@ ARIANE_VERILATOR_FLAGS = \
 	--unroll-count 256 \
 	-Werror-PINMISSING \
 	-Werror-IMPLICIT \
-	-Wno-fatal \
 	-Wno-PINCONNECTEMPTY \
 	-Wno-ASSIGNDLY \
 	-Wno-DECLFILENAME \
@@ -91,9 +90,11 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1
 VERILATOR_NONCC_OPTS = \
 	$(TIMESCALE_OPTS) \
 	--top-module $(VLOG_MODEL) \
+	-Wno-fatal \
 	$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
 	--output-split 10000 \
 	--output-split-cfuncs 100 \
+	--max-num-width 1048576 \
 	-f $(sim_common_files) \
 	$(sim_vsrcs)
 

tests/Makefile

@@ -5,7 +5,7 @@ LDFLAGS= -static
 
 include libgloss.mk
 
-PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd spiflashread spiflashwrite
+PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd nvdla spiflashread spiflashwrite
 
 spiflash.img: spiflash.py
 	python3 $<