efabless

Here are 7 public repositories matching this topic...

edabk-hust / edabk_brain_soc

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

verilog soc snn efabless openlane chatgpt chatgpt4

Updated Feb 18, 2024
Verilog

mattvenn / wrapped_project_template

Star

Template project for the Zero to ASIC course group ASIC application

template google asic efabless sky130

Updated Jan 3, 2023
Verilog

mattvenn / zero_to_asic_mpw6

Star

MPW6 submission from the Zero to ASIC Course

asic verilog efabless sky130 mpw6

Updated Jun 22, 2022
Verilog

rejunity / zero-to-asic-wrapped-parallax

Star

Tiny experimental ASIC design for efabless/OpenLane fab.

asic fpga verilog efabless openlane

Updated Nov 16, 2021
Verilog

kisek / rvcore_chip1

Star

asic efabless

Updated Sep 5, 2022
Verilog

kisek / rvcore_chip2

Star

RISC-V Processor

asic efabless

Updated Dec 7, 2023
Verilog

fguzman82 / upb_natalius_soc

Star

8 bit RISC Processor for SKY 130nm process

processor-architecture verilog risc efabless sky130

Updated Jun 17, 2024
Verilog

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efabless

Here are 7 public repositories matching this topic...

edabk-hust / edabk_brain_soc

mattvenn / wrapped_project_template

mattvenn / zero_to_asic_mpw6

rejunity / zero-to-asic-wrapped-parallax

kisek / rvcore_chip1

kisek / rvcore_chip2

fguzman82 / upb_natalius_soc

Improve this page

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