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alu

Here are 48 public repositories matching this topic...

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

spam-1

Johnlon / spam-1

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

design cpu vhdl assembler verilog rom ttl alu 8bit cmos verilog-components logism homebrew-cpu

Updated Aug 27, 2023
Verilog

RomeoMe5 / DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

princeofpython / Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

cpu processor verilog pipelining alu risc-v riscv32

Updated May 1, 2021
Verilog

AsadiAhmad / ALU-8Bit

ALU Verilog Project calculate add, subtract, increment, decrement, multiply

hardware verilog alu

Updated Mar 16, 2025
Verilog

OpenBanboo / High-Performance-ALU

RTL Design and Implementation of High Performance Algorithm Logic Units

algorithm computer arithmetic alu

Updated Oct 1, 2019
Verilog

Robin-WZQ / 32bit-ALU

32位ALU加法器（verilog），支持加法并行方式和真串行方式，6种运算（算术运算和逻辑运算），能够输出结果和4个标志位。

verilog vivado alu

Updated Apr 16, 2023
Verilog

luk3Sky / Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

processor-architecture alu hdl verilog-hdl verilog-project

Updated Jan 28, 2019
Verilog

EmreKumas / Processor_Design

This is an implementation of a simple CPU in Logisim and Verilog.

cpu instructions assembler alu logisim modelsim control-unit cpu-design cpu-simulation register-file data-memory address-memory

Updated Jan 11, 2019
Verilog

Didula98 / Building-a-Simple-Processor

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

cpu instructions verilog alu gtkwave instruction-set-architecture

Updated Jul 8, 2022
Verilog

armixz / ALU-Design-and-Development

32 bits ALU include 16 commands to run/Verilog Code (.v) + Digital Circuit (.circ)

verilog circuit alu verilog-hdl

Updated Nov 27, 2021
Verilog

shawntsai0312 / NTUEE_COMPUTER_ARCHITECTURE_23FALL_HOMEWORK

NTUEE Computer Architecture 23Fall Homework

assembly rtl verilog ntu computer-architecture alu risc-v ntuee

Updated May 12, 2024
Verilog

ayushgupta98 / ALU

An efficient multiplier and Accumulator (MAC) unit to do operations like multiplication & addition on numbers stored in RAM unit attached to it.

verilog alu verilog-hdl modified-booth-algorithm carry-look-ahead-adder

Updated Dec 5, 2018
Verilog

Jamboii / verilog-assignments

Source code for various Verilog-based projects and assignments

verilog alu adder combinational-logic

Updated Nov 8, 2018
Verilog

AnjanaSenanayake / verilog-model-for-8bit-processor

An implementation of a processor with basic components coded in verilog

register processor verilog computer-architecture alu opcode verilog-hdl digital-design

Updated Sep 9, 2017
Verilog

naforoutan / DLC-Project

This is my DLC project.

verilog alu dlc verilog-project

Updated Jan 29, 2025
Verilog

Dakshay-S / 8-Bit-Processor-in-VHDL

VHDL(Verilog Hardware Description Language) is a programming language using which one can simulate hardware circuits

controller vhdl verilog microprocessor mux add alu risc hdl multiplexer sub 8-bit program-counter bitwise-or bitwise-and

Updated Jul 30, 2020
Verilog

sjkeller / smart-sensors-project

Verilog implementations of different simple tasks

fpga verilog alu hdl verilog-hdl yosys ice40 spi-protocol verilog-project

Updated Oct 10, 2022
Verilog

aarya-arun / DDCO-Shift-Register-and-ALU

ALU register implementation and added functionalities for shifts

verilog mux alu shift-register msb-bits

Updated Apr 30, 2020
Verilog

NadaElokaily / ALU-

verilog ALU

verilog mux alu

Updated Apr 20, 2018
Verilog

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