UVM Test bench for a 8-bit ALU
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Dec 24, 2020 - SystemVerilog
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alu
Here are 12 public repositories matching this topic...
Simple RISC-V Pipelined processor implemented on SystemVerilog.
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Jan 8, 2025 - SystemVerilog
32 bits CLA(Carry Lookahead Adder) and ALU RTL and verification. 32位块间超前的超前进位加法器及ALU设计与验证
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Oct 25, 2022 - SystemVerilog
This is a modified version of the 32-bit MIPS microprocessor. Please refer to "manual.pdf" for more information.
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Jan 23, 2017 - SystemVerilog
This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.
cpu fpga simulation processor riscv verilog assembly-language vivado systemverilog alu risc-v registers fpga-programming riscvprocessor
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Mar 2, 2025 - SystemVerilog
A simple arithmetic logic unit (ALU) with System verilog
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Aug 21, 2020 - SystemVerilog
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May 3, 2023 - SystemVerilog
SystemVerlilog-Projects
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Mar 30, 2021 - SystemVerilog
An ALU implementation in System Verilog. Course project: Code upon request.
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Jan 4, 2022 - SystemVerilog
10-bit MDR (Multiplication, division and square root calculator) implemented for the FPGA DE2-115 and for a ModelSim simulation. Coded in System Verilog ⚙️
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Feb 17, 2022 - SystemVerilog
This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic
verilog fulladder systemverilog mux logic-gates alu multiplexer computerorganization inverter arithmetic-logic-unit
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Nov 2, 2024 - SystemVerilog
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