CSE341 Project 2- Explorations in Datapath Design

Alain Schaerer
University at Buffalo
B.A Computer Science with math minor
University at Buffalo Football\

Project Summary\

This project is an implementation of an ALU. This ALU only implements the "add" function.

Project Objective\

*Half Adder in System Verilog
*Full Adder in System Verilog
*Ripple-Carry Adder using 32 FUll Adders *5 total testcases (5 pairs of 32 bit numbers)
*Analysis
*Report\

Implementation Summary\

*Input: Two 32 bit numbers. Carry in hardcoded as 0. *Output: One 32 bit number that represents the two 32 bit numbers added together
*System Verilog will be used to design a Half Adder, A Full Adder, and a ripple carry adder
*The Ripple Carry Adder will be designed with the usage of the half adder and full adder modules.
*EDAPLayground will be used to implement and test the project