minor rtl edits (#1193)

stnolting · Mar 1, 2025 · d28aa12 · d28aa12
2 parents 3cd192e + f5a5e7e
commit d28aa12
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 01.03.2025 | 1.11.1.7 | minor rtl / coding style edits (fixing a Vivado 2024.2 synthesis issue) | [#1193](https://github.com/stnolting/neorv32/pull/1193) |
 | 23.02.2025 | 1.11.1.6 | source-out CPU counters into a new rtl file (`neorv32_cpu_counters.vhd`) | [#1192](https://github.com/stnolting/neorv32/pull/1192) |
 | 22.02.2025 | 1.11.1.5 | minor rtl edits and cleanups | [#1191](https://github.com/stnolting/neorv32/pull/1191) |
 | 20.02.2025 | 1.11.1.4 | :bug: fix bug in `Zalrsc` ISA extension's bus request decoding | [#1190](https://github.com/stnolting/neorv32/pull/1190) |

diff --git a/rtl/core/neorv32_bus.vhd b/rtl/core/neorv32_bus.vhd
@@ -347,6 +347,9 @@ end neorv32_bus_gateway;
 architecture neorv32_bus_gateway_rtl of neorv32_bus_gateway is
 
   -- port select --
+  constant a_lo_c : natural := index_size_f(A_SIZE);
+  constant b_lo_c : natural := index_size_f(B_SIZE);
+  constant c_lo_c : natural := index_size_f(C_SIZE);
   signal port_sel : std_ulogic_vector(3 downto 0);
 
   -- port enable list --
@@ -375,9 +378,9 @@ begin
 
   -- Address Section Decoder ----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  port_sel(0) <= '1' when A_EN and (req_i.addr(31 downto index_size_f(A_SIZE)) = A_BASE(31 downto index_size_f(A_SIZE))) else '0';
-  port_sel(1) <= '1' when B_EN and (req_i.addr(31 downto index_size_f(B_SIZE)) = B_BASE(31 downto index_size_f(B_SIZE))) else '0';
-  port_sel(2) <= '1' when C_EN and (req_i.addr(31 downto index_size_f(C_SIZE)) = C_BASE(31 downto index_size_f(C_SIZE))) else '0';
+  port_sel(0) <= '1' when A_EN and (req_i.addr(31 downto a_lo_c) = A_BASE(31 downto a_lo_c)) else '0';
+  port_sel(1) <= '1' when B_EN and (req_i.addr(31 downto b_lo_c) = B_BASE(31 downto b_lo_c)) else '0';
+  port_sel(2) <= '1' when C_EN and (req_i.addr(31 downto c_lo_c) = C_BASE(31 downto c_lo_c)) else '0';
 
   -- accesses to the "void" are redirected to the X port --
   port_sel(3) <= '1' when X_EN and (port_sel(2 downto 0) = "000") else '0';

diff --git a/rtl/core/neorv32_cpu_alu.vhd b/rtl/core/neorv32_cpu_alu.vhd
@@ -155,7 +155,7 @@ begin
   csr_o <= csr_rdata_fpu or csr_rdata_cfu;
 
   -- shift amount --
-  cp_shamt <= opb(index_size_f(XLEN)-1 downto 0);
+  cp_shamt <= opb(cp_shamt'left downto 0);
 
 
   -- ALU[I]-Opcode Co-Processor: Shifter Unit (Base ISA) ------------------------------------

diff --git a/rtl/core/neorv32_cpu_cp_bitmanip.vhd b/rtl/core/neorv32_cpu_cp_bitmanip.vhd
@@ -11,7 +11,7 @@
 -- -------------------------------------------------------------------------------- --
 -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
 -- Copyright (c) NEORV32 contributors.                                              --
--- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  --
+-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  --
 -- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
 -- SPDX-License-Identifier: BSD-3-Clause                                            --
 -- ================================================================================ --
@@ -304,7 +304,7 @@ begin
       bs_level(i+1)(XLEN-1 downto XLEN-(2**i)) <= bs_level(i)((2**i)-1 downto 0)  when (bs_shift(i) = '1') else bs_level(i)(XLEN-1 downto XLEN-(2**i));
       bs_level(i+1)((XLEN-(2**i))-1 downto 0)  <= bs_level(i)(XLEN-1 downto 2**i) when (bs_shift(i) = '1') else bs_level(i)((XLEN-(2**i))-1 downto 0);
     end generate;
-    shifter.sreg <= bs_level(index_size_f(XLEN)); -- rol/ror[i]
+    shifter.sreg <= bs_level(bs_level'left); -- rol/ror[i]
 
     -- population count --
     shifter.bcnt <= std_ulogic_vector(to_unsigned(popcount_f(rs1_reg), shifter.bcnt'length)); -- cpop

diff --git a/rtl/core/neorv32_cpu_cp_shifter.vhd b/rtl/core/neorv32_cpu_cp_shifter.vhd
@@ -6,7 +6,7 @@
 -- -------------------------------------------------------------------------------- --
 -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
 -- Copyright (c) NEORV32 contributors.                                              --
--- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  --
+-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  --
 -- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
 -- SPDX-License-Identifier: BSD-3-Clause                                            --
 -- ================================================================================ --
@@ -135,7 +135,7 @@ begin
       if (rstn_i = '0') then
         bs_result <= (others => '0');
       elsif rising_edge(clk_i) then
-        bs_result <= bs_level(index_size_f(XLEN));
+        bs_result <= bs_level(bs_level'left);
       end if;
     end process barrel_shifter_buf;
 

diff --git a/rtl/core/neorv32_cpu_frontend.vhd b/rtl/core/neorv32_cpu_frontend.vhd
@@ -46,6 +46,7 @@ architecture neorv32_cpu_frontend_rtl of neorv32_cpu_frontend is
     pc      : std_ulogic_vector(XLEN-1 downto 0);
     resp    : std_ulogic; -- bus response
     priv    : std_ulogic; -- fetch privilege level
+    halted  : std_ulogic; -- instruction fetch has halted
   end record;
   signal fetch : fetch_t;
 
@@ -115,7 +116,7 @@ begin
         when others => -- S_RESTART: set new start address
         -- ------------------------------------------------------------
           fetch.restart <= '0'; -- restart done
-          fetch.pc      <= ctrl_i.pc_nxt; -- initialize from PC incl. 16-bit-alignment bit
+          fetch.pc      <= ctrl_i.pc_nxt; -- initialize from PC
           fetch.priv    <= ctrl_i.cpu_priv; -- set new privilege level
           fetch.state   <= S_REQUEST;
 
@@ -140,16 +141,19 @@ begin
   ipb.we(0) <= '1' when (fetch.state = S_PENDING) and (fetch.resp = '1') and ((fetch.pc(1) = '0') or (not RVC_EN)) else '0';
   ipb.we(1) <= '1' when (fetch.state = S_PENDING) and (fetch.resp = '1') else '0';
 
+  -- instruction fetch has halted --
+  fetch.halted <= '1' when (fetch.state = S_REQUEST) and (ipb.free /= "11") else '0';
+
   -- bus access meta data --
   ibus_req_o.data  <= (others => '0');  -- read-only
   ibus_req_o.ben   <= (others => '0');  -- read-only
   ibus_req_o.rw    <= '0';              -- read-only
   ibus_req_o.src   <= '1';              -- always "instruction fetch" access
   ibus_req_o.priv  <= fetch.priv;       -- current effective privilege level
-  ibus_req_o.debug <= ctrl_i.cpu_debug; -- debug mode, valid without STB being set
+  ibus_req_o.debug <= ctrl_i.cpu_debug; -- CPU is in debug mode
   ibus_req_o.amo   <= '0';              -- cannot be an atomic memory operation
   ibus_req_o.amoop <= (others => '0');  -- cannot be an atomic memory operation
-  ibus_req_o.fence <= ctrl_i.if_fence;  -- fence operation, valid without STB being set
+  ibus_req_o.fence <= ctrl_i.if_fence;  -- fence request, valid without STB being set ("out-of-band" signal)
 
 
   -- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
@@ -158,11 +162,11 @@ begin
   for i in 0 to 1 generate -- low half-word + high half-word (incl. status bits)
     prefetch_buffer_inst: entity neorv32.neorv32_fifo
     generic map (
-      FIFO_DEPTH => 2,                   -- number of IPB entries; has to be a power of two, min 2
-      FIFO_WIDTH => ipb.wdata(i)'length, -- size of data elements in FIFO
-      FIFO_RSYNC => false,               -- we NEED to read data asynchronously
-      FIFO_SAFE  => false,               -- no safe access required (ensured by FIFO-external logic)
-      FULL_RESET => false                -- no need for a full hardware reset
+      FIFO_DEPTH => 2,     -- number of IPB entries; has to be a power of two, min 2
+      FIFO_WIDTH => 17,    -- size of data elements in FIFO
+      FIFO_RSYNC => false, -- we NEED to read data asynchronously
+      FIFO_SAFE  => false, -- no safe access required (ensured by FIFO-external logic)
+      FULL_RESET => false  -- no need for a full hardware reset
     )
     port map (
       -- control and status --
@@ -274,12 +278,13 @@ begin
   end generate;
 
 
-  -- assemble output bus --
+  -- Instruction Interface to CPU Back-End (Execution) --------------------------------------
+  -- -------------------------------------------------------------------------------------------
   frontend_o.valid  <= issue.valid(1) or issue.valid(0);
   frontend_o.instr  <= issue.instr;
   frontend_o.compr  <= issue.compr;
   frontend_o.error  <= issue.error;
-  frontend_o.halted <= '1' when (fetch.state = S_REQUEST) and (ipb.free /= "11") else '0';
+  frontend_o.halted <= fetch.halted;
 
 
 end neorv32_cpu_frontend_rtl;
diff --git a/rtl/core/neorv32_dmem.vhd b/rtl/core/neorv32_dmem.vhd
@@ -6,7 +6,7 @@
 -- -------------------------------------------------------------------------------- --
 -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
 -- Copyright (c) NEORV32 contributors.                                              --
--- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  --
+-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  --
 -- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
 -- SPDX-License-Identifier: BSD-3-Clause                                            --
 -- ================================================================================ --
@@ -35,6 +35,9 @@ architecture neorv32_dmem_rtl of neorv32_dmem is
   -- alternative memory description style --
   constant alt_style_c : boolean := false; -- [TIP] enable this if synthesis fails to infer block RAM
 
+  -- highest address bit --
+  constant addr_hi_c : natural := index_size_f(DMEM_SIZE/4)+1;
+
   -- local signals --
   signal rdata         : std_ulogic_vector(31 downto 0);
   signal rden          : std_ulogic;
@@ -107,7 +110,7 @@ begin
   end generate;
 
   -- word aligned access address --
-  addr <= unsigned(bus_req_i.addr(index_size_f(DMEM_SIZE/4)+1 downto 2));
+  addr <= unsigned(bus_req_i.addr(addr_hi_c downto 2));
 
 
   -- Bus Response ---------------------------------------------------------------------------

diff --git a/rtl/core/neorv32_imem.vhd b/rtl/core/neorv32_imem.vhd
@@ -6,7 +6,7 @@
 -- -------------------------------------------------------------------------------- --
 -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
 -- Copyright (c) NEORV32 contributors.                                              --
--- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  --
+-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  --
 -- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
 -- SPDX-License-Identifier: BSD-3-Clause                                            --
 -- ================================================================================ --
@@ -37,6 +37,9 @@ architecture neorv32_imem_rtl of neorv32_imem is
   -- alternative memory description style --
   constant alt_style_c : boolean := false; -- [TIP] enable this if synthesis fails to infer block RAM
 
+  -- highest address bit --
+  constant addr_hi_c : natural := index_size_f(IMEM_SIZE/4)+1;
+
   -- ROM - initialized with executable code --
   constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image_c, IMEM_SIZE/4);
 
@@ -95,7 +98,7 @@ begin
   end generate;
 
   -- word aligned access address --
-  addr <= unsigned(bus_req_i.addr(index_size_f(IMEM_SIZE/4)+1 downto 2));
+  addr <= unsigned(bus_req_i.addr(addr_hi_c downto 2));
 
 
   -- Implement IMEM as non-initialized RAM --------------------------------------------------

diff --git a/rtl/core/neorv32_neoled.vhd b/rtl/core/neorv32_neoled.vhd
@@ -54,6 +54,9 @@ architecture neorv32_neoled_rtl of neorv32_neoled is
   constant ctrl_tx_full_c  : natural := 30; -- r/-: TX FIFO is full
   constant ctrl_tx_busy_c  : natural := 31; -- r/-: serial TX engine busy when set
 
+  -- helpers --
+  constant log2_fifo_size_c : natural := index_size_f(FIFO_DEPTH);
+
   -- control register --
   type ctrl_t is record
     enable   : std_ulogic;
@@ -139,7 +142,7 @@ begin
           bus_rsp_o.data(ctrl_strobe_c)                        <= ctrl.strobe;
           bus_rsp_o.data(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_prsc;
           bus_rsp_o.data(ctrl_irq_conf_c)                      <= ctrl.irq_conf or bool_to_ulogic_f(boolean(FIFO_DEPTH = 1)); -- tie to one if FIFO_DEPTH is 1
-          bus_rsp_o.data(ctrl_bufs_3_c  downto ctrl_bufs_0_c)  <= std_ulogic_vector(to_unsigned(index_size_f(FIFO_DEPTH), 4));
+          bus_rsp_o.data(ctrl_bufs_3_c  downto ctrl_bufs_0_c)  <= std_ulogic_vector(to_unsigned(log2_fifo_size_c, 4));
           bus_rsp_o.data(ctrl_t_tot_4_c downto ctrl_t_tot_0_c) <= ctrl.t_total;
           bus_rsp_o.data(ctrl_t_0h_4_c  downto ctrl_t_0h_0_c)  <= ctrl.t0_high;
           bus_rsp_o.data(ctrl_t_1h_4_c  downto ctrl_t_1h_0_c)  <= ctrl.t1_high;

diff --git a/rtl/core/neorv32_onewire.vhd b/rtl/core/neorv32_onewire.vhd
@@ -73,6 +73,9 @@ architecture neorv32_onewire_rtl of neorv32_onewire is
   constant cmd_byt_c : std_ulogic_vector(1 downto 0) := "10"; -- trigger full-byte transmission
   constant cmd_rst_c : std_ulogic_vector(1 downto 0) := "11"; -- trigger reset pulse and sample presence
 
+  -- helpers --
+  constant log2_fifo_size_c : natural := index_size_f(ONEWIRE_FIFO);
+
   -- control register --
   type ctrl_t is record
     enable    : std_ulogic;
@@ -148,7 +151,7 @@ begin
           bus_rsp_o.data(ctrl_prsc1_c downto ctrl_prsc0_c)     <= ctrl.clk_prsc;
           bus_rsp_o.data(ctrl_clkdiv7_c downto ctrl_clkdiv0_c) <= ctrl.clk_div;
           --
-          bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(ONEWIRE_FIFO), 4));
+          bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(log2_fifo_size_c, 4));
           --
           bus_rsp_o.data(ctrl_tx_full_c)  <= not fifo.tx_free;
           bus_rsp_o.data(ctrl_rx_avail_c) <= fifo.rx_avail;

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110106"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110107"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

diff --git a/rtl/core/neorv32_sdi.vhd b/rtl/core/neorv32_sdi.vhd
@@ -57,6 +57,9 @@ architecture neorv32_sdi_rtl of neorv32_sdi is
   --
   constant ctrl_cs_active_c    : natural := 31; -- r/-: chip-select is active when set
 
+  -- helpers --
+  constant log2_fifo_size_c : natural := index_size_f(RTX_FIFO);
+
   -- control register (see bit definitions above) --
   type ctrl_t is record
     enable       : std_ulogic;
@@ -139,7 +142,7 @@ begin
           if (bus_req_i.addr(2) = '0') then -- control register
             bus_rsp_o.data(ctrl_en_c) <= ctrl.enable;
             --
-            bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(RTX_FIFO), 4));
+            bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(log2_fifo_size_c, 4));
             --
             bus_rsp_o.data(ctrl_irq_rx_avail_c) <= ctrl.irq_rx_avail;
             bus_rsp_o.data(ctrl_irq_rx_half_c)  <= ctrl.irq_rx_half;

diff --git a/rtl/core/neorv32_slink.vhd b/rtl/core/neorv32_slink.vhd
@@ -79,6 +79,10 @@ architecture neorv32_slink_rtl of neorv32_slink is
   constant ctrl_tx_fifo_size2_c : natural := 30; -- r/-: log2(TX fifo size), bit 2
   constant ctrl_tx_fifo_size3_c : natural := 31; -- r/-: log2(TX fifo size), bit 3 (msb)
 
+  -- helpers --
+  constant log2_rx_fifo_c : natural := index_size_f(SLINK_RX_FIFO);
+  constant log2_tx_fifo_c : natural := index_size_f(SLINK_TX_FIFO);
+
   -- control register --
   type ctrl_t is record
     enable                      : std_ulogic;
@@ -178,8 +182,8 @@ begin
               bus_rsp_o.data(ctrl_irq_tx_nhalf_c)  <= ctrl.irq_tx_nhalf;
               bus_rsp_o.data(ctrl_irq_tx_nfull_c)  <= ctrl.irq_tx_nfull;
               --
-              bus_rsp_o.data(ctrl_rx_fifo_size3_c downto ctrl_rx_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_RX_FIFO), 4));
-              bus_rsp_o.data(ctrl_tx_fifo_size3_c downto ctrl_tx_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_TX_FIFO), 4));
+              bus_rsp_o.data(ctrl_rx_fifo_size3_c downto ctrl_rx_fifo_size0_c) <= std_ulogic_vector(to_unsigned(log2_rx_fifo_c, 4));
+              bus_rsp_o.data(ctrl_tx_fifo_size3_c downto ctrl_tx_fifo_size0_c) <= std_ulogic_vector(to_unsigned(log2_tx_fifo_c, 4));
             when "01" => -- routing information
               bus_rsp_o.data(3 downto 0) <= route_dst;
               bus_rsp_o.data(7 downto 4) <= route_src;

diff --git a/rtl/core/neorv32_spi.vhd b/rtl/core/neorv32_spi.vhd
@@ -65,6 +65,9 @@ architecture neorv32_spi_rtl of neorv32_spi is
   constant ctrl_cs_active_c    : natural := 30; -- r/-: a chip-select line is active when set
   constant ctrl_busy_c         : natural := 31; -- r/-: spi phy busy or tx fifo not empty yet
 
+  -- helpers --
+  constant log2_fifo_size_c : natural := index_size_f(IO_SPI_FIFO);
+
   -- control register --
   type ctrl_t is record
     enable       : std_ulogic;
@@ -163,7 +166,7 @@ begin
             bus_rsp_o.data(ctrl_irq_tx_nhalf_c) <= ctrl.irq_tx_nhalf;
             bus_rsp_o.data(ctrl_irq_idle_c)     <= ctrl.irq_idle;
             --
-            bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(IO_SPI_FIFO), 4));
+            bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(log2_fifo_size_c, 4));
             --
             bus_rsp_o.data(ctrl_cs_active_c) <= rtx_engine.cs_ctrl(3);
             bus_rsp_o.data(ctrl_busy_c)      <= rtx_engine.busy or tx_fifo.avail;