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Feature - Swaps parameters of sub reg, imm
and removes neg
#489
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Codecov Report
@@ Coverage Diff @@
## main #489 +/- ##
==========================================
- Coverage 89.69% 89.65% -0.05%
==========================================
Files 23 23
Lines 10109 10126 +17
==========================================
+ Hits 9067 9078 +11
- Misses 1042 1048 +6
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18 tasks
alessandrod
reviewed
Jul 28, 2023
src/interpreter.rs
Outdated
@@ -264,7 +264,11 @@ impl<'a, 'b, V: Verifier, C: ContextObject> Interpreter<'a, 'b, V, C> { | |||
// BPF_ALU class | |||
ebpf::ADD32_IMM => self.reg[dst] = (self.reg[dst] as i32).wrapping_add(insn.imm as i32) as u64, | |||
ebpf::ADD32_REG => self.reg[dst] = (self.reg[dst] as i32).wrapping_add(self.reg[src] as i32) as u64, | |||
ebpf::SUB32_IMM => self.reg[dst] = (self.reg[dst] as i32).wrapping_sub(insn.imm as i32) as u64, | |||
ebpf::SUB32_IMM => if self.executable.get_sbpf_version().enable_neg() { |
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I would use a more explicit swap_sub_operands() or something instead of
piggybacking on enable_neg
. These flags are cheap and having an explicit one
makes the logic easier to follow.
And I would also add an if enable_neg() to the ::NEG_* handlers again for
explicitness, and so it doesn't have to rely on the verifier doing things at a distance
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alessandrod
approved these changes
Jul 28, 2023
sub reg, imm
and removes neg
10 tasks
nvjle
pushed a commit
to anza-xyz/llvm-project
that referenced
this pull request
Dec 16, 2023
Following the alterations made in solana-labs/rbpf#489, this PR removes the neg instructions and changes the semantics of sub when one of the operands is an immediate. sub r1, 2 now means r1 = 2 - r1, instead of r1 = r1 - 2. neg r1 is represented as r1 = 0 - r1. This is the second task in solana-labs/solana#34250.
LucasSte
added a commit
to LucasSte/llvm-project
that referenced
this pull request
Jan 31, 2024
Following the alterations made in solana-labs/rbpf#489, this PR removes the neg instructions and changes the semantics of sub when one of the operands is an immediate. sub r1, 2 now means r1 = 2 - r1, instead of r1 = r1 - 2. neg r1 is represented as r1 = 0 - r1. This is the second task in solana-labs/solana#34250.
LucasSte
added a commit
to anza-xyz/llvm-project
that referenced
this pull request
Feb 16, 2024
Following the alterations made in solana-labs/rbpf#489, this PR removes the neg instructions and changes the semantics of sub when one of the operands is an immediate. sub r1, 2 now means r1 = 2 - r1, instead of r1 = r1 - 2. neg r1 is represented as r1 = 0 - r1. This is the second task in solana-labs/solana#34250.
LucasSte
added a commit
to LucasSte/llvm-project
that referenced
this pull request
Jun 28, 2024
Following the alterations made in solana-labs/rbpf#489, this PR removes the neg instructions and changes the semantics of sub when one of the operands is an immediate. sub r1, 2 now means r1 = 2 - r1, instead of r1 = r1 - 2. neg r1 is represented as r1 = 0 - r1. This is the second task in solana-labs/solana#34250.
LucasSte
added a commit
to anza-xyz/llvm-project
that referenced
this pull request
Aug 19, 2024
Following the alterations made in solana-labs/rbpf#489, this PR removes the neg instructions and changes the semantics of sub when one of the operands is an immediate. sub r1, 2 now means r1 = 2 - r1, instead of r1 = r1 - 2. neg r1 is represented as r1 = 0 - r1. This is the second task in solana-labs/solana#34250.
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Currently the instruction
sub reg, imm
is useless because it can be encoded asadd reg, -imm
instead.If we swap the parameters of
sub reg, imm
fromreg = reg - imm
toreg = imm - reg
it becomes a useful instruction which would otherwise require two instructions to encode. Furthermore, theneg
instruction can be removed as well because it can be encoded assub reg, 0
(reg = 0 - reg
) instead.It seems that llvm is never emitting
sub reg, imm
for registers other thanR11
(which was already addressed in #488).For
neg
the instruction info in llvm would need to be patched here:https://github.com/solana-labs/llvm-project/blob/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF/SBFInstrInfo.td#L319