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#OpenToWork
C/C++/Python TDD RISCV RTL RayTracing AudioSynth...
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darkriscv
darkriscv PublicForked from darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog
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max1000-tutorial
max1000-tutorial PublicForked from vpecanins/max1000-tutorial
Tutorial and example projects for the Arrow MAX1000 FPGA board
Verilog
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Tutorials_MiSTer
Tutorials_MiSTer PublicForked from alanswx/Tutorials_MiSTer
Tutorials from the mist project converted to MiSTer
C++
502 contributions in the last year
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Contribution activity
June 2025
Created 1 repository
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nsauzede/bitwise-examples
Rust
This contribution was made on Jun 27
Opened 3 pull requests in 3 repositories
zesterer/bitwise-examples
1
open
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Fix typo
This contribution was made on Jun 27
nsauzede/darkriscv
1
open
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Fix big endian - WIP set leds early
This contribution was made on Jun 25
darklife/darkriscv
1
closed
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Test CI
This contribution was made on Jun 25
3
contributions
in private repositories
Jun 2 – Jun 27