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nand2marionand2mario
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add m60k pll
1 parent 3d9a353 commit 22c2334

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‎gbatang_m60k.gprj

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<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW5AT-60B" pn="GW5AT-LV60PG484AC1/I0">gw5at60b-002</Device>
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<FileList>
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<File path="src/common/dpram32_block.v" type="file.verilog" enable="1"/>
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<File path="src/common/dpram_block.v" type="file.verilog" enable="1"/>
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<File path="src/common/dual_clk_fifo.v" type="file.verilog" enable="1"/>
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<File path="src/common/eprocreg_gba.sv" type="file.verilog" enable="1"/>
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<File path="src/cpu/gba_cpu.v" type="file.verilog" enable="1"/>
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<File path="src/cpu/gba_cpu_thumbdecoder.v" type="file.verilog" enable="1"/>
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<File path="src/cpu/gba_interrupts.v" type="file.verilog" enable="1"/>
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<File path="src/gba2hdmi.sv" type="file.verilog" enable="1"/>
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<File path="src/gbatang_top.sv" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_drawer_merge.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_drawer_mode0.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_drawer_mode2.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_drawer_mode345.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_drawer_obj.sv" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_gpu.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_gpu_colorshade.sv" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_gpu_drawer.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_gpu_timing.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_timer.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/gba_timer_module.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/linebuffer.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/vram_hi.v" type="file.verilog" enable="1"/>
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<File path="src/gpu/vram_lo.v" type="file.verilog" enable="1"/>
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<File path="src/hdmi/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/audio_info_frame.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/audio_sample_packet.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/hdmi.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/packet_assembler.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/packet_picker.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/serializer.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
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<File path="src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
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<File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/iosys.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/picorv32.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/simplespimaster.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/simpleuart.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/spi_master.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/spiflash.v" type="file.verilog" enable="1"/>
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<File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/>
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<File path="src/m138k/fb.v" type="file.verilog" enable="1"/>
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<File path="src/m60k/pll_27.v" type="file.verilog" enable="1"/>
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<File path="src/m60k/pll_33.v" type="file.verilog" enable="1"/>
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<File path="src/m60k/pll_74.v" type="file.verilog" enable="1"/>
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<File path="src/memory/gba_dma.v" type="file.verilog" enable="1"/>
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<File path="src/memory/gba_dma_module.sv" type="file.verilog" enable="1"/>
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<File path="src/memory/gba_eeprom.sv" type="file.verilog" enable="1"/>
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<File path="src/memory/gba_flash_sram.sv" type="file.verilog" enable="1"/>
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<File path="src/memory/gba_memory.sv" type="file.verilog" enable="1"/>
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<File path="src/memory/mem_eeprom.v" type="file.verilog" enable="1"/>
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<File path="src/memory/mem_iwram.v" type="file.verilog" enable="1"/>
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<File path="src/memory/rv_sdram_adapter.v" type="file.verilog" enable="1"/>
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<File path="src/memory/sdram_gba.v" type="file.verilog" enable="1"/>
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<File path="src/peripherals/controller_ds2.sv" type="file.verilog" enable="1"/>
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<File path="src/peripherals/dualshock_controller.v" type="file.verilog" enable="1"/>
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<File path="src/peripherals/gba_joypad.v" type="file.verilog" enable="1"/>
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<File path="src/sound/gba_sound.v" type="file.verilog" enable="1"/>
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<File path="src/sound/gba_sound_ch1.v" type="file.verilog" enable="1"/>
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<File path="src/sound/gba_sound_ch3.v" type="file.verilog" enable="1"/>
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<File path="src/sound/gba_sound_ch4.v" type="file.verilog" enable="1"/>
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<File path="src/sound/gba_sound_dma.v" type="file.verilog" enable="1"/>
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<File path="src/m138k/m138k.cst" type="file.cst" enable="1"/>
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<File path="src/m138kpro.cst" type="file.cst" enable="0"/>
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<File path="src/gbatang.sdc" type="file.sdc" enable="1"/>
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<File path="src/eeprom.gao" type="file.gao" enable="0"/>
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<File path="src/gbatang.gao" type="file.gao" enable="0"/>
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<File path="src/gpu.gao" type="file.gao" enable="0"/>
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<File path="src/iosys.gao" type="file.gao" enable="0"/>
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</FileList>
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</Project>

‎src/m60k/config.v

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`ifndef CONFIG_H
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`define CONFIG_H
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`define M60K
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`endif CONFIG_H

‎src/m60k/pll_27.ipc

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[General]
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ipc_version=4
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file=pll_27
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module=pll_27
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target_device=gw5at60b-002
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type=clock_plladv
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version=1.0
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[Config]
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AdvancedMode=false
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ClkfbDivideFactorStatic=true
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ClkfbDivideFactorStaticValue=1
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ClkfbInternal=true
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ClkfboutExpectedFrequency=400
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ClkfboutTolerance=0.0
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ClkfboutVCODivideFactorStatic=true
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ClkfboutVCODivideFactorStaticValue=27
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ClkfboutVCOFractionalDivideFactorStaticValue=0
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ClkinClockFrequency=50
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ClkinDividerFactorStatic=true
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ClkinDividerFactorStaticValue=1
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ClkinDividerReset=false
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Clkou1BPhaseStatic=true
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Clkou2BPhaseStatic=true
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Clkou3BPhaseStatic=true
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Clkout0Bypass=false
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Clkout0DutyCycleDynamic=false
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Clkout0DutyCycleDynamicValue=0
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Clkout0DutyCycleStatic=true
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Clkout0DutyTrimStatic=true
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Clkout0DutyTrimStaticFalling=false
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Clkout0DutyTrimStaticRising=true
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Clkout0DutyTrimStaticStep=0
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Clkout0ExpectedFrequency=27
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Clkout0PhaseDynamic=false
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Clkout0PhaseStatic=true
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Clkout0PhaseStaticValue=0
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Clkout0Tolerance=0.0
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Clkout0VCODivideFactorStatic=true
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Clkout0VCODivideFactorStaticValue=50
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Clkout0VCOFractionalDivideFactorStaticValue=0
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Clkout1Bypass=false
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Clkout1DutyCycleDynamic=false
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Clkout1DutyCycleDynamicValue=0
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Clkout1DutyCycleStatic=true
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Clkout1DutyTrimStatic=true
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Clkout1DutyTrimStaticFalling=false
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Clkout1DutyTrimStaticRising=true
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Clkout1DutyTrimStaticStep=0
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Clkout1ExpectedFrequency=400
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Clkout1PhaseDynamic=false
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Clkout1PhaseStaticValue=0
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Clkout1Tolerance=0.0
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Clkout1VCODivideFactorStatic=true
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Clkout1VCODivideFactorStaticValue=8
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Clkout2Bypass=false
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Clkout2DutyCycleDynamic=false
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Clkout2DutyCycleDynamicValue=0
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Clkout2DutyCycleStatic=true
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Clkout2DutyTrimStatic=true
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Clkout2DutyTrimStaticFalling=false
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Clkout2DutyTrimStaticRising=true
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Clkout2DutyTrimStaticStep=0
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Clkout2ExpectedFrequency=400
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Clkout2PhaseDynamic=false
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Clkout2PhaseStaticValue=0
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Clkout2Tolerance=0.0
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Clkout2VCODivideFactorStatic=true
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Clkout2VCODivideFactorStaticValue=8
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Clkout3Bypass=false
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Clkout3DutyCycleDynamic=false
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Clkout3DutyCycleDynamicValue=0
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Clkout3DutyCycleStatic=true
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Clkout3DutyTrimStatic=true
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Clkout3DutyTrimStaticFalling=false
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Clkout3DutyTrimStaticRising=true
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Clkout3DutyTrimStaticStep=0
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Clkout3ExpectedFrequency=400
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Clkout3PhaseDynamic=false
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Clkout3PhaseStaticValue=0
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Clkout3Tolerance=0.0
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Clkout3VCODivideFactorStatic=true
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Clkout3VCODivideFactorStaticValue=8
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Clkout4Bypass=false
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Clkout4DutyCycleDynamic=false
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Clkout4DutyCycleDynamicValue=0
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Clkout4DutyCycleStatic=true
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Clkout4ExpectedFrequency=400
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Clkout4PhaseDynamic=false
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Clkout4PhaseStatic=true
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Clkout4PhaseStaticValue=0
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Clkout4Tolerance=0.0
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Clkout4VCODivideFactorStatic=true
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Clkout4VCODivideFactorStaticValue=8
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Clkout5Bypass=false
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Clkout5DutyCycleDynamic=false
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Clkout5DutyCycleDynamicValue=0
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Clkout5DutyCycleStatic=true
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Clkout5ExpectedFrequency=400
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Clkout5PhaseDynamic=false
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Clkout5PhaseStatic=true
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Clkout5PhaseStaticValue=0
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Clkout5Tolerance=0.0
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Clkout5VCODivideFactorStatic=true
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Clkout5VCODivideFactorStaticValue=8
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Clkout6Bypass=false
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Clkout6DutyCycleDynamic=false
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Clkout6DutyCycleDynamicValue=0
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Clkout6DutyCycleStatic=true
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Clkout6ExpectedFrequency=400
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Clkout6PhaseDynamic=false
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Clkout6PhaseStatic=true
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Clkout6PhaseStaticValue=0
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Clkout6Tolerance=0.0
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Clkout6VCODivideFactorStatic=true
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Clkout6VCODivideFactorStaticValue=8
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ClkoutDividerReset=false
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EnableCascade=false
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EnableClkfbout=false
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EnableClkout0Divider=false
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EnableClkout1=false
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EnableClkout1Divider=false
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EnableClkout2=false
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EnableClkout2Divider=false
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EnableClkout3=false
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EnableClkout3Divider=false
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EnableClkout4=false
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EnableClkout4Divider=false
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EnableClkout5=false
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EnableClkout5Divider=false
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EnableClkout6=false
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EnableClkout6Divider=false
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EnableLock=false
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EnableSsc=false
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GeneralMode=true
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ICPSELStatic=true
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ICPSELStaticValue=X
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LANG=0
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LPFCAPStaticValue=C0
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LPFRESStaticValue=X
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LPFSELStatic=true
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PLLPowerDown=false
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PLLReset=false
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clkfbExternal=false
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clkfbExternalValue=

‎src/m60k/pll_27.mod

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-series GW5AT
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-device GW5AT-60
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-device_version B
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-package PBGA484A
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-part_number GW5AT-LV60PG484AC1/I0
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-mod_name pll_27
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-file_name pll_27
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-path Y:/mdtang/src/m60k/
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-type PLL_ADV
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-file_type vlg
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-ssc false
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-rst false
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-rst_pwd false
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-rst_i false
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-rst_o false
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-fclkin 50
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-idiv_sel 1
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-clkfb_sel 0
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-fbdiv_sel 1
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-en_lock false
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-dyn_dpa_en false
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-clkout0_bypass false
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-odiv0_sel 50
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-odiv0_frac_sel 0
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-clkout0_dt_dir 1
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-clkout0_dt_step 0
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-dyn_pe0_sel false
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-clkout0_pe_coarse 0
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-clkout0_pe_fine 0
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-de0_en false
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-clkout0_dt_dir 1
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-clkout0_dt_step 0
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-en_clkout1 false
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-en_clkout2 false
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-en_clkout3 false
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-en_clkout4 false
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-en_clkout5 false
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-en_clkout6 false
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-en_clkfbout false
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-mdiv_sel 27
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-mdiv_frac_sel 0

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