[dvsim,questa] DRAFT questa fixes

[hcallahan-lowrisc]

DO NOT MERGE

[lmg260a]

New topic: line 213 of hw/ip/entropy_src/rtl/entropy_src.sv has:

stub_hw2reg.debug_status.main_sm_state.d = 8'b01110110;

stub_hw2reg is defined on line 89 of the same file:

entropy_src_hw2reg_t stub_hw2reg;

entropy_src_hw2reg_t is defined in entropy_src_reg_pkg.sv, lines 743-786

  typedef struct packed {
     ....
     entropy_src_hw2reg_debug_status_reg_t debug_status; // [80:70]
    ... } entropy_src_hw2reg_t;

entropy_src_hw2reg_debug_status_reg_t is defined in entropy_src_reg_pkg.sv, lines 555:580

  typedef struct packed {
    ...
      struct packed {
      logic        d;
    } main_sm_idle;
  } entropy_src_hw2reg_debug_status_reg_t;

So in debug_status, I see a "main_sm_idle" but not main_sm_state.
I compared the generated to original and the files are identical.
There's no obvious `defines that would affect this (to me). So I suspect there's some higher-level configuration that I've got wrong. Can you possibly help?

My build command is:
util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx
I have to generate VCS, then port to questa, because

util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson \
		-i chip_sw_uart_tx_rx \
		-n \
		--tool questa 

won't run.

[lmg260a]

For questa simulation, using these defines:
+define+TOP_LEVEL_DV
+define+UVM
+define+UVM_NO_DEPRECATED
+define+UVM_REGEX_NO_DPI
+define+UVM_REG_ADDR_WIDTH=32
+define+UVM_REG_DATA_WIDTH=64
+define+UVM_REG_BYTENABLE_WIDTH=8
+define+SIMULATION
+define+DUT_HIER=tb.dut
Please review.