Support I/O interfaces for Embedded FPGAs #114

tangxifan · 2020-11-03T01:41:12Z

Users can define circuit model of an input pad or output pad, beyond a GPIO cell, enabling the I/O interface for embedded FPGAs
Remove signal initialization in the auto-generated HDL codes for logic gates, i.e., AND, OR, MUX2

…nal initalization

tangxifan added 18 commits November 2, 2020 11:54

[Arch] Add VPR architecture with partial pin equivalence

795b30f

[Arch] Add openfpga architecture file for constrained pin equivalence

f86f43d

[Test] Add test case for embedded I/O

bc00dee

[Test] Deploy test case to CI

a346c52

[Arch] Rename architecture files for embedded I/Os

8c81900

[Test] Update test case with the new arch name

65ca53a

[Arch] Update arch with true embedded I/O definition

a7e7fa2

[Tool] Relax checking codes for embedded I/O circuit models

e850dd5

[Arch] Bug fixed in embedded FPGA architecture

55b77ac

[HDL] Add HDL codes for embedded I/Os

2f237a6

[Tool] Force inout port to be mandatory for I/O cells

f1ce816

[HDL] Bug fix in I/O HDL code

7e9e0ec

[Arch] Patch embedded I/O example architecture

c512644

[Arch] Patch embedded IO architecture by forcing only 1 pad per block

3b49e6d

[Tool] Relex logic block checking codes to skip zero-capacity nodes

1fd899e

[Tool] Split io location mapping builder from fabric builder

e4d974c

[Tool] Auto-generated gate Verilog netlist should not contain any sig…

1e47203

…nal initalization

[HDL] Bug fix in the GP output pad

c036c87

LNIS-Projects approved these changes Nov 3, 2020

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LNIS-Projects merged commit 5d41cc6 into master Nov 3, 2020

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