[SVE ACLE] Allow default zero initialisation for svcount_t.

[paulwalker-arm]

This matches the behaviour of the other SVE ACLE types.

[llvmbot]

@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-llvm-ir

@llvm/pr-subscribers-clang

Author: Paul Walker (paulwalker-arm)

Changes

This matches the behaviour of the other SVE ACLE types.

---

Full diff: https://github.com/llvm/llvm-project/pull/69321.diff

4 Files Affected:

• (modified) clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp (+18)
• (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+6)
• (modified) llvm/lib/IR/Type.cpp (+2-1)
• (modified) llvm/test/CodeGen/AArch64/sve-zeroinit.ll (+7)

diff --git a/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp b/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
index 2088e80acfc80f4..464275f164c2a54 100644
--- a/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
+++ b/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
@@ -55,6 +55,7 @@
 // CHECK-NEXT:    [[B8:%.*]] = alloca <vscale x 16 x i1>, align 2
 // CHECK-NEXT:    [[B8X2:%.*]] = alloca <vscale x 32 x i1>, align 2
 // CHECK-NEXT:    [[B8X4:%.*]] = alloca <vscale x 64 x i1>, align 2
+// CHECK-NEXT:    [[CNT:%.*]] = alloca target("aarch64.svcount"), align 2
 // CHECK-NEXT:    store <vscale x 16 x i8> zeroinitializer, ptr [[S8]], align 16
 // CHECK-NEXT:    store <vscale x 8 x i16> zeroinitializer, ptr [[S16]], align 16
 // CHECK-NEXT:    store <vscale x 4 x i32> zeroinitializer, ptr [[S32]], align 16
@@ -106,6 +107,7 @@
 // CHECK-NEXT:    store <vscale x 16 x i1> zeroinitializer, ptr [[B8]], align 2
 // CHECK-NEXT:    store <vscale x 32 x i1> zeroinitializer, ptr [[B8X2]], align 2
 // CHECK-NEXT:    store <vscale x 64 x i1> zeroinitializer, ptr [[B8X4]], align 2
+// CHECK-NEXT:    store target("aarch64.svcount") zeroinitializer, ptr [[CNT]], align 2
 // CHECK-NEXT:    ret void
 //
 void test_locals(void) {
@@ -164,6 +166,8 @@ void test_locals(void) {
   __SVBool_t b8{};
   __clang_svboolx2_t b8x2{};
   __clang_svboolx4_t b8x4{};
+
+  __SVCount_t cnt{};
 }
 
 // CHECK-LABEL: define dso_local void @_Z12test_copy_s8u10__SVInt8_t
@@ -879,3 +883,17 @@ void test_copy_b8x2(__clang_svboolx2_t a) {
 void test_copy_b8x4(__clang_svboolx4_t a) {
   __clang_svboolx4_t b{a};
 }
+
+// CHECK-LABEL: define dso_local void @_Z13test_copy_cntu11__SVCount_t
+// CHECK-SAME: (target("aarch64.svcount") [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca target("aarch64.svcount"), align 2
+// CHECK-NEXT:    [[B:%.*]] = alloca target("aarch64.svcount"), align 2
+// CHECK-NEXT:    store target("aarch64.svcount") [[A]], ptr [[A_ADDR]], align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = load target("aarch64.svcount"), ptr [[A_ADDR]], align 2
+// CHECK-NEXT:    store target("aarch64.svcount") [[TMP0]], ptr [[B]], align 2
+// CHECK-NEXT:    ret void
+//
+void test_copy_cnt(__SVCount_t a) {
+  __SVCount_t b{a};
+}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4bb0ba6f083109b..eabc76334fae1f2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1738,6 +1738,12 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
     if (const auto *NC = dyn_cast<NoCFIValue>(C))
       return getValue(NC->getGlobalValue());
 
+    if (VT == MVT::aarch64svcount) {
+      assert(C->isNullValue() && "Can only zero this target type!");
+      return DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT,
+                         DAG.getConstant(0, getCurSDLoc(), MVT::nxv16i1));
+    }
+
     VectorType *VecTy = cast<VectorType>(V->getType());
 
     // Now that we know the number and type of the elements, get that number of
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index 97febcd99b4114f..006278d16484c1c 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -841,7 +841,8 @@ static TargetTypeInfo getTargetTypeInfo(const TargetExtType *Ty) {
 
   // Opaque types in the AArch64 name space.
   if (Name == "aarch64.svcount")
-    return TargetTypeInfo(ScalableVectorType::get(Type::getInt1Ty(C), 16));
+    return TargetTypeInfo(ScalableVectorType::get(Type::getInt1Ty(C), 16),
+                          TargetExtType::HasZeroInit);
 
   return TargetTypeInfo(Type::getVoidTy(C));
 }
diff --git a/llvm/test/CodeGen/AArch64/sve-zeroinit.ll b/llvm/test/CodeGen/AArch64/sve-zeroinit.ll
index c436bb7f822b7a3..eab39d0ef402526 100644
--- a/llvm/test/CodeGen/AArch64/sve-zeroinit.ll
+++ b/llvm/test/CodeGen/AArch64/sve-zeroinit.ll
@@ -86,3 +86,10 @@ define <vscale x 16 x i1> @test_zeroinit_16xi1() {
 ; CHECK-NEXT:  ret
   ret <vscale x 16 x i1> zeroinitializer
 }
+
+define target("aarch64.svcount") @test_zeroinit_svcount() "target-features"="+sme2" {
+; CHECK-LABEL: test_zeroinit_svcount
+; CHECK:       pfalse p0.b
+; CHECK-NEXT:  ret
+  ret target("aarch64.svcount") zeroinitializer
+}

[kmclaughlin-arm]

LGTM!

[dlee992]

Hi, @paulwalker-arm .
I wanna ask whether we should insert NodeMap[V] = here for caching the mapping between them? Or I neglect sth? (I am still a beginner in LLVM community)

return NodeMap[V] = DAG.getNode(...

If you think it's good to have, I can open a PR to add this as my first PR!

[paulwalker-arm]

I agree, it looks like an omission on my part when landing the original work. If you're happy to fix then that would be great, otherwise just let me know and I'll follow up.