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[RISCV] Fix inline asm error for block address #66640

Merged
merged 1 commit into from
Sep 19, 2023
Merged

[RISCV] Fix inline asm error for block address #66640

merged 1 commit into from
Sep 19, 2023

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wangpc-pp
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After commit cedf2ea, RISCVMergeBaseOffset can handle BlockAddress
currently. But we didn't handle it in PrintAsmMemoryOperand so we
get invalid operand in inline asm error.

This patch fixes the error.

@wangpc-pp
[RISCV] Fix inline asm error for block address
27d8e35 
After commit cedf2ea, `RISCVMergeBaseOffset` can handle `BlockAddress`
currently. But we didn't handle it in `PrintAsmMemoryOperand` so we
get `invalid operand in inline asm` error.

This patch fixes the error.
@llvmbot
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llvmbot commented Sep 18, 2023

@llvm/pr-subscribers-backend-risc-v

Changes

After commit cedf2ea, RISCVMergeBaseOffset can handle BlockAddress
currently. But we didn't handle it in PrintAsmMemoryOperand so we
get invalid operand in inline asm error.

This patch fixes the error.

Patch is 36.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66640.diff

2 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll (+416-96)
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 17326c68f0bd363..526520e6c5267df 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -236,7 +236,7 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
   // RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand).
   if (!AddrReg.isReg())
     return true;
-  if (!Offset.isImm() && !Offset.isGlobal())
+  if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isBlockAddress())
     return true;
 
   MCOperand MCO;
@@ -245,7 +245,7 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 
   if (Offset.isImm())
     OS << MCO.getImm();
-  else if (Offset.isGlobal())
+  else if (Offset.isGlobal() || Offset.isBlockAddress())
     OS << *MCO.getExpr();
   OS << "(" << RISCVInstPrinter::getRegisterName(AddrReg.getReg()) << ")";
   return false;
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll b/llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
index a74572518cd0331..1f12d500f3945bf 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
@@ -358,6 +358,166 @@ define void @constraint_m_with_extern_weak_global_3() nounwind {
   ret void
 }
 
+define void @constraint_m_with_local_1() nounwind {
+; RV32I-LABEL: constraint_m_with_local_1:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:  .Ltmp0: # Block address taken
+; RV32I-NEXT:  # %bb.1: # %label
+; RV32I-NEXT:    lui a0, %hi(.Ltmp0)
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    lw zero, %lo(.Ltmp0)(a0)
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_m_with_local_1:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:  .Ltmp0: # Block address taken
+; RV64I-NEXT:  # %bb.1: # %label
+; RV64I-NEXT:    lui a0, %hi(.Ltmp0)
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    lw zero, %lo(.Ltmp0)(a0)
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+;
+; RV32I-MEDIUM-LABEL: constraint_m_with_local_1:
+; RV32I-MEDIUM:       # %bb.0: # %entry
+; RV32I-MEDIUM-NEXT:  .Ltmp0: # Block address taken
+; RV32I-MEDIUM-NEXT:  # %bb.1: # %label
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi6:
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp0)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
+; RV32I-MEDIUM-NEXT:    #APP
+; RV32I-MEDIUM-NEXT:    lw zero, 0(a0)
+; RV32I-MEDIUM-NEXT:    #NO_APP
+; RV32I-MEDIUM-NEXT:    ret
+;
+; RV64I-MEDIUM-LABEL: constraint_m_with_local_1:
+; RV64I-MEDIUM:       # %bb.0: # %entry
+; RV64I-MEDIUM-NEXT:  .Ltmp0: # Block address taken
+; RV64I-MEDIUM-NEXT:  # %bb.1: # %label
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi6:
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp0)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
+; RV64I-MEDIUM-NEXT:    #APP
+; RV64I-MEDIUM-NEXT:    lw zero, 0(a0)
+; RV64I-MEDIUM-NEXT:    #NO_APP
+; RV64I-MEDIUM-NEXT:    ret
+entry:
+  br label %label
+
+label:
+  tail call void asm sideeffect "lw zero, $0", "*m"(ptr elementtype(ptr) blockaddress(@constraint_m_with_local_1, %label))
+  ret void
+}
+
+define void @constraint_m_with_local_2() nounwind {
+; RV32I-LABEL: constraint_m_with_local_2:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:  .Ltmp1: # Block address taken
+; RV32I-NEXT:  # %bb.1: # %label
+; RV32I-NEXT:    lui a0, %hi(.Ltmp1)
+; RV32I-NEXT:    addi a0, a0, %lo(.Ltmp1)
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    lw zero, 4(a0)
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_m_with_local_2:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:  .Ltmp1: # Block address taken
+; RV64I-NEXT:  # %bb.1: # %label
+; RV64I-NEXT:    lui a0, %hi(.Ltmp1)
+; RV64I-NEXT:    addi a0, a0, %lo(.Ltmp1)
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    lw zero, 4(a0)
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+;
+; RV32I-MEDIUM-LABEL: constraint_m_with_local_2:
+; RV32I-MEDIUM:       # %bb.0: # %entry
+; RV32I-MEDIUM-NEXT:  .Ltmp1: # Block address taken
+; RV32I-MEDIUM-NEXT:  # %bb.1: # %label
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi7:
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp1)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
+; RV32I-MEDIUM-NEXT:    #APP
+; RV32I-MEDIUM-NEXT:    lw zero, 4(a0)
+; RV32I-MEDIUM-NEXT:    #NO_APP
+; RV32I-MEDIUM-NEXT:    ret
+;
+; RV64I-MEDIUM-LABEL: constraint_m_with_local_2:
+; RV64I-MEDIUM:       # %bb.0: # %entry
+; RV64I-MEDIUM-NEXT:  .Ltmp1: # Block address taken
+; RV64I-MEDIUM-NEXT:  # %bb.1: # %label
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi7:
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp1)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
+; RV64I-MEDIUM-NEXT:    #APP
+; RV64I-MEDIUM-NEXT:    lw zero, 4(a0)
+; RV64I-MEDIUM-NEXT:    #NO_APP
+; RV64I-MEDIUM-NEXT:    ret
+entry:
+  br label %label
+
+label:
+  call void asm "lw zero, $0", "*m"(ptr nonnull elementtype(i32) getelementptr inbounds (i8, ptr blockaddress(@constraint_m_with_local_2, %label), i32 4))
+  ret void
+}
+
+define void @constraint_m_with_local_3() nounwind {
+; RV32I-LABEL: constraint_m_with_local_3:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:  .Ltmp2: # Block address taken
+; RV32I-NEXT:  # %bb.1: # %label
+; RV32I-NEXT:    lui a0, %hi(.Ltmp2)
+; RV32I-NEXT:    addi a0, a0, %lo(.Ltmp2)
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    lw zero, 2000(a0)
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_m_with_local_3:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:  .Ltmp2: # Block address taken
+; RV64I-NEXT:  # %bb.1: # %label
+; RV64I-NEXT:    lui a0, %hi(.Ltmp2)
+; RV64I-NEXT:    addi a0, a0, %lo(.Ltmp2)
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    lw zero, 2000(a0)
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+;
+; RV32I-MEDIUM-LABEL: constraint_m_with_local_3:
+; RV32I-MEDIUM:       # %bb.0: # %entry
+; RV32I-MEDIUM-NEXT:  .Ltmp2: # Block address taken
+; RV32I-MEDIUM-NEXT:  # %bb.1: # %label
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi8:
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp2)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi8)
+; RV32I-MEDIUM-NEXT:    #APP
+; RV32I-MEDIUM-NEXT:    lw zero, 2000(a0)
+; RV32I-MEDIUM-NEXT:    #NO_APP
+; RV32I-MEDIUM-NEXT:    ret
+;
+; RV64I-MEDIUM-LABEL: constraint_m_with_local_3:
+; RV64I-MEDIUM:       # %bb.0: # %entry
+; RV64I-MEDIUM-NEXT:  .Ltmp2: # Block address taken
+; RV64I-MEDIUM-NEXT:  # %bb.1: # %label
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi8:
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.Ltmp2)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi8)
+; RV64I-MEDIUM-NEXT:    #APP
+; RV64I-MEDIUM-NEXT:    lw zero, 2000(a0)
+; RV64I-MEDIUM-NEXT:    #NO_APP
+; RV64I-MEDIUM-NEXT:    ret
+entry:
+  br label %label
+
+label:
+  call void asm "lw zero, $0", "*m"(ptr nonnull elementtype(i32) getelementptr inbounds (i8, ptr blockaddress(@constraint_m_with_local_3, %label), i32 2000))
+  ret void
+}
+
 define void @constraint_m_with_multi_operands() nounwind {
 ; RV32I-LABEL: constraint_m_with_multi_operands:
 ; RV32I:       # %bb.0:
@@ -377,9 +537,9 @@ define void @constraint_m_with_multi_operands() nounwind {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_m_with_multi_operands:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi6:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi9:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi9)
 ; RV32I-MEDIUM-NEXT:    #APP
 ; RV32I-MEDIUM-NEXT:    sw zero, 0(a0); sw zero, 0(a0)
 ; RV32I-MEDIUM-NEXT:    #NO_APP
@@ -387,9 +547,9 @@ define void @constraint_m_with_multi_operands() nounwind {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_m_with_multi_operands:
 ; RV64I-MEDIUM:       # %bb.0:
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi6:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi9:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi6)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi9)
 ; RV64I-MEDIUM-NEXT:    #APP
 ; RV64I-MEDIUM-NEXT:    sw zero, 0(a0); sw zero, 0(a0)
 ; RV64I-MEDIUM-NEXT:    #NO_APP
@@ -423,9 +583,9 @@ define void @constraint_m_with_multi_asm() nounwind {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_m_with_multi_asm:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi7:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi10:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi10)
 ; RV32I-MEDIUM-NEXT:    #APP
 ; RV32I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV32I-MEDIUM-NEXT:    #NO_APP
@@ -436,9 +596,9 @@ define void @constraint_m_with_multi_asm() nounwind {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_m_with_multi_asm:
 ; RV64I-MEDIUM:       # %bb.0:
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi7:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi10:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi7)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi10)
 ; RV64I-MEDIUM-NEXT:    #APP
 ; RV64I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV64I-MEDIUM-NEXT:    #NO_APP
@@ -456,12 +616,12 @@ define i32 @constraint_m_with_callbr_multi_operands(i32 %a) {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(eg)
 ; RV32I-NEXT:    #APP
-; RV32I-NEXT:    sw zero, %lo(eg)(a1); sw zero, %lo(eg)(a1); beqz a0, .LBB11_2
+; RV32I-NEXT:    sw zero, %lo(eg)(a1); sw zero, %lo(eg)(a1); beqz a0, .LBB14_2
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:  # %bb.1: # %normal
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB11_2: # Block address taken
+; RV32I-NEXT:  .LBB14_2: # Block address taken
 ; RV32I-NEXT:    # %fail
 ; RV32I-NEXT:    # Label of block must be emitted
 ; RV32I-NEXT:    li a0, 1
@@ -471,12 +631,12 @@ define i32 @constraint_m_with_callbr_multi_operands(i32 %a) {
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    lui a1, %hi(eg)
 ; RV64I-NEXT:    #APP
-; RV64I-NEXT:    sw zero, %lo(eg)(a1); sw zero, %lo(eg)(a1); beqz a0, .LBB11_2
+; RV64I-NEXT:    sw zero, %lo(eg)(a1); sw zero, %lo(eg)(a1); beqz a0, .LBB14_2
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:  # %bb.1: # %normal
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB11_2: # Block address taken
+; RV64I-NEXT:  .LBB14_2: # Block address taken
 ; RV64I-NEXT:    # %fail
 ; RV64I-NEXT:    # Label of block must be emitted
 ; RV64I-NEXT:    li a0, 1
@@ -484,16 +644,16 @@ define i32 @constraint_m_with_callbr_multi_operands(i32 %a) {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_m_with_callbr_multi_operands:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi8:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi11:
 ; RV32I-MEDIUM-NEXT:    auipc a1, %pcrel_hi(eg)
-; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi8)
+; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi11)
 ; RV32I-MEDIUM-NEXT:    #APP
-; RV32I-MEDIUM-NEXT:    sw zero, 0(a1); sw zero, 0(a1); beqz a0, .LBB11_2
+; RV32I-MEDIUM-NEXT:    sw zero, 0(a1); sw zero, 0(a1); beqz a0, .LBB14_2
 ; RV32I-MEDIUM-NEXT:    #NO_APP
 ; RV32I-MEDIUM-NEXT:  # %bb.1: # %normal
 ; RV32I-MEDIUM-NEXT:    li a0, 0
 ; RV32I-MEDIUM-NEXT:    ret
-; RV32I-MEDIUM-NEXT:  .LBB11_2: # Block address taken
+; RV32I-MEDIUM-NEXT:  .LBB14_2: # Block address taken
 ; RV32I-MEDIUM-NEXT:    # %fail
 ; RV32I-MEDIUM-NEXT:    # Label of block must be emitted
 ; RV32I-MEDIUM-NEXT:    li a0, 1
@@ -501,16 +661,16 @@ define i32 @constraint_m_with_callbr_multi_operands(i32 %a) {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_m_with_callbr_multi_operands:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi8:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi11:
 ; RV64I-MEDIUM-NEXT:    auipc a1, %pcrel_hi(eg)
-; RV64I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi8)
+; RV64I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi11)
 ; RV64I-MEDIUM-NEXT:    #APP
-; RV64I-MEDIUM-NEXT:    sw zero, 0(a1); sw zero, 0(a1); beqz a0, .LBB11_2
+; RV64I-MEDIUM-NEXT:    sw zero, 0(a1); sw zero, 0(a1); beqz a0, .LBB14_2
 ; RV64I-MEDIUM-NEXT:    #NO_APP
 ; RV64I-MEDIUM-NEXT:  # %bb.1: # %normal
 ; RV64I-MEDIUM-NEXT:    li a0, 0
 ; RV64I-MEDIUM-NEXT:    ret
-; RV64I-MEDIUM-NEXT:  .LBB11_2: # Block address taken
+; RV64I-MEDIUM-NEXT:  .LBB14_2: # Block address taken
 ; RV64I-MEDIUM-NEXT:    # %fail
 ; RV64I-MEDIUM-NEXT:    # Label of block must be emitted
 ; RV64I-MEDIUM-NEXT:    li a0, 1
@@ -530,16 +690,16 @@ define i32 @constraint_m_with_multi_callbr_asm(i32 %a) {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, %hi(eg)
 ; RV32I-NEXT:    #APP
-; RV32I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB12_3
+; RV32I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB15_3
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:  # %bb.1: # %normal0
 ; RV32I-NEXT:    #APP
-; RV32I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB12_3
+; RV32I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB15_3
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:  # %bb.2: # %normal1
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB12_3: # Block address taken
+; RV32I-NEXT:  .LBB15_3: # Block address taken
 ; RV32I-NEXT:    # %fail
 ; RV32I-NEXT:    # Label of block must be emitted
 ; RV32I-NEXT:    li a0, 1
@@ -549,16 +709,16 @@ define i32 @constraint_m_with_multi_callbr_asm(i32 %a) {
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    lui a1, %hi(eg)
 ; RV64I-NEXT:    #APP
-; RV64I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB12_3
+; RV64I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB15_3
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:  # %bb.1: # %normal0
 ; RV64I-NEXT:    #APP
-; RV64I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB12_3
+; RV64I-NEXT:    sw zero, %lo(eg)(a1); beqz a0, .LBB15_3
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:  # %bb.2: # %normal1
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB12_3: # Block address taken
+; RV64I-NEXT:  .LBB15_3: # Block address taken
 ; RV64I-NEXT:    # %fail
 ; RV64I-NEXT:    # Label of block must be emitted
 ; RV64I-NEXT:    li a0, 1
@@ -566,20 +726,20 @@ define i32 @constraint_m_with_multi_callbr_asm(i32 %a) {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_m_with_multi_callbr_asm:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi9:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi12:
 ; RV32I-MEDIUM-NEXT:    auipc a1, %pcrel_hi(eg)
-; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi9)
+; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi12)
 ; RV32I-MEDIUM-NEXT:    #APP
-; RV32I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB12_3
+; RV32I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB15_3
 ; RV32I-MEDIUM-NEXT:    #NO_APP
 ; RV32I-MEDIUM-NEXT:  # %bb.1: # %normal0
 ; RV32I-MEDIUM-NEXT:    #APP
-; RV32I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB12_3
+; RV32I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB15_3
 ; RV32I-MEDIUM-NEXT:    #NO_APP
 ; RV32I-MEDIUM-NEXT:  # %bb.2: # %normal1
 ; RV32I-MEDIUM-NEXT:    li a0, 0
 ; RV32I-MEDIUM-NEXT:    ret
-; RV32I-MEDIUM-NEXT:  .LBB12_3: # Block address taken
+; RV32I-MEDIUM-NEXT:  .LBB15_3: # Block address taken
 ; RV32I-MEDIUM-NEXT:    # %fail
 ; RV32I-MEDIUM-NEXT:    # Label of block must be emitted
 ; RV32I-MEDIUM-NEXT:    li a0, 1
@@ -587,20 +747,20 @@ define i32 @constraint_m_with_multi_callbr_asm(i32 %a) {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_m_with_multi_callbr_asm:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi9:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi12:
 ; RV64I-MEDIUM-NEXT:    auipc a1, %pcrel_hi(eg)
-; RV64I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi9)
+; RV64I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.Lpcrel_hi12)
 ; RV64I-MEDIUM-NEXT:    #APP
-; RV64I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB12_3
+; RV64I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB15_3
 ; RV64I-MEDIUM-NEXT:    #NO_APP
 ; RV64I-MEDIUM-NEXT:  # %bb.1: # %normal0
 ; RV64I-MEDIUM-NEXT:    #APP
-; RV64I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB12_3
+; RV64I-MEDIUM-NEXT:    sw zero, 0(a1); beqz a0, .LBB15_3
 ; RV64I-MEDIUM-NEXT:    #NO_APP
 ; RV64I-MEDIUM-NEXT:  # %bb.2: # %normal1
 ; RV64I-MEDIUM-NEXT:    li a0, 0
 ; RV64I-MEDIUM-NEXT:    ret
-; RV64I-MEDIUM-NEXT:  .LBB12_3: # Block address taken
+; RV64I-MEDIUM-NEXT:  .LBB15_3: # Block address taken
 ; RV64I-MEDIUM-NEXT:    # %fail
 ; RV64I-MEDIUM-NEXT:    # Label of block must be emitted
 ; RV64I-MEDIUM-NEXT:    li a0, 1
@@ -730,9 +890,9 @@ define void @constraint_o_with_global_1() nounwind {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_o_with_global_1:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi10:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi13:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi10)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi13)
 ; RV32I-MEDIUM-NEXT:    #APP
 ; RV32I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV32I-MEDIUM-NEXT:    #NO_APP
@@ -740,9 +900,9 @@ define void @constraint_o_with_global_1() nounwind {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_o_with_global_1:
 ; RV64I-MEDIUM:       # %bb.0:
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi10:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi13:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi10)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi13)
 ; RV64I-MEDIUM-NEXT:    #APP
 ; RV64I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV64I-MEDIUM-NEXT:    #NO_APP
@@ -772,9 +932,9 @@ define void @constraint_o_with_global_2() nounwind {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_o_with_global_2:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi11:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi14:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi11)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi14)
 ; RV32I-MEDIUM-NEXT:    #APP
 ; RV32I-MEDIUM-NEXT:    sw zero, 4(a0)
 ; RV32I-MEDIUM-NEXT:    #NO_APP
@@ -782,9 +942,9 @@ define void @constraint_o_with_global_2() nounwind {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_o_with_global_2:
 ; RV64I-MEDIUM:       # %bb.0:
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi11:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi14:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi11)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi14)
 ; RV64I-MEDIUM-NEXT:    #APP
 ; RV64I-MEDIUM-NEXT:    sw zero, 4(a0)
 ; RV64I-MEDIUM-NEXT:    #NO_APP
@@ -814,9 +974,9 @@ define void @constraint_o_with_global_3() nounwind {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_o_with_global_3:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi12:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi15:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg+8000)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi12)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi15)
 ; RV32I-MEDIUM-NEXT:    #APP
 ; RV32I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV32I-MEDIUM-NEXT:    #NO_APP
@@ -824,9 +984,9 @@ define void @constraint_o_with_global_3() nounwind {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_o_with_global_3:
 ; RV64I-MEDIUM:       # %bb.0:
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi12:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi15:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(eg+8000)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi12)
+; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi15)
 ; RV64I-MEDIUM-NEXT:    #APP
 ; RV64I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV64I-MEDIUM-NEXT:    #NO_APP
@@ -854,9 +1014,9 @@ define void @constraint_o_with_extern_weak_global_1() nounwind {
 ;
 ; RV32I-MEDIUM-LABEL: constraint_o_with_extern_weak_global_1:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .Lpcrel_hi13:
+; RV32I-MEDIUM-NEXT:  .Lpcrel_hi16:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %got_pcrel_hi(ewg)
-; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi13)(a0)
+; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi16)(a0)
 ; RV32I-MEDIUM-NEXT:    #APP
 ; RV32I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV32I-MEDIUM-NEXT:    #NO_APP
@@ -864,9 +1024,9 @@ define void @constraint_o_with_extern_weak_global_1() nounwind {
 ;
 ; RV64I-MEDIUM-LABEL: constraint_o_with_extern_weak_global_1:
 ; RV64I-MEDIUM:       # %bb.0:
-; RV64I-MEDIUM-NEXT:  .Lpcrel_hi13:
+; RV64I-MEDIUM-NEXT:  .Lpcrel_hi16:
 ; RV64I-MEDIUM-NEXT:    auipc a0, %got_pcrel_hi(ewg)
-; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi13)(a0)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi16)(a0)
 ; RV64I-MEDIUM-NEXT:    #APP
 ; RV64I-MEDIUM-NEXT:    sw zero, 0(a0)
 ; RV64I-MEDIUM-NEXT:    #NO_APP
@@ -89...
[truncated]

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Optimizations will be done in my rework of [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.

asb
asb approved these changes Sep 18, 2023
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LGTM.

@wangpc-pp wangpc-pp merged commit 3017545 into llvm:main Sep 19, 2023
@wangpc-pp wangpc-pp deleted the main-inline-asm-block-address branch September 19, 2023 03:47
ZijunZhaoCCK pushed a commit to ZijunZhaoCCK/llvm-project that referenced this pull request Sep 19, 2023
@wangpc-pp @ZijunZhaoCCK
[RISCV] Fix inline asm error for block address (llvm#66640)
a8d1584 
After commit cedf2ea, `RISCVMergeBaseOffset` can handle `BlockAddress`
currently. But we didn't handle it in `PrintAsmMemoryOperand` so we
get `invalid operand in inline asm` error.

This patch fixes the error.
This was referenced Sep 19, 2023
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@asb asb asb approved these changes

@jrtc27 jrtc27 Awaiting requested review from jrtc27

@kito-cheng kito-cheng Awaiting requested review from kito-cheng

@topperc topperc Awaiting requested review from topperc

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@wangpc-pp @llvmbot @asb