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[RISCV] Add Smrnmi extension #111668

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merged 26 commits into from
Oct 25, 2024
Merged

[RISCV] Add Smrnmi extension #111668

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c7a9b55
Update RISCVSystemOperands.td
dong-miao Oct 9, 2024
91125a1
Update machine-csr-names.s
dong-miao Oct 9, 2024
6014139
Update riscv-target-features.c
dong-miao Oct 9, 2024
8706286
Update RISCVUsage.rst
dong-miao Oct 9, 2024
6844754
Update RISCVFeatures.td
dong-miao Oct 9, 2024
7922fbb
Update attributes.ll
dong-miao Oct 9, 2024
c8fccb5
Update attributes.ll
dong-miao Oct 9, 2024
3d6f0fe
Update attribute-arch.s
dong-miao Oct 9, 2024
805fd8a
Update RISCVISAInfoTest.cpp
dong-miao Oct 9, 2024
35588a3
Update riscv-target-features.c
dong-miao Oct 9, 2024
f497950
Update riscv-target-features.c
dong-miao Oct 9, 2024
7db01e7
Update RISCVInstrInfo.td
dong-miao Oct 9, 2024
29eaa52
Update priv-valid.s
dong-miao Oct 9, 2024
3c5f6d1
Update priv-invalid.s
dong-miao Oct 9, 2024
1858bed
Update RISCVFeatures.td
dong-miao Oct 21, 2024
dedaf01
Update RISCVFeatures.td
dong-miao Oct 21, 2024
3086afc
Update RISCVInstrInfo.td
dong-miao Oct 21, 2024
95567b3
Update RISCVSystemOperands.td
dong-miao Oct 21, 2024
88dfe2b
Update priv-invalid.s
dong-miao Oct 21, 2024
1350674
Update priv-valid.s
dong-miao Oct 21, 2024
116aa08
Create smrnmi-invalid.s
dong-miao Oct 21, 2024
e077536
Create smrnmi-valid.s
dong-miao Oct 21, 2024
6249ffb
Update llvm/docs/RISCVUsage.rst
dong-miao Oct 22, 2024
2452b33
Merge branch 'main' into develop
dong-miao Oct 23, 2024
5a58844
Update attribute-arch.s
dong-miao Oct 24, 2024
769d395
Update print-supported-extensions-riscv.c
dong-miao Oct 24, 2024
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1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -120,6 +120,7 @@
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
// CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts)
// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
// CHECK-NEXT: ssccfg 1.0 'Ssccfg' (Counter Configuration Supervisor Level)
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9 changes: 9 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -30,6 +30,7 @@
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smrnmi {{.*$}}
// CHECK-NOT: __riscv_smstateen {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
// CHECK-NOT: __riscv_ssccfg {{.*$}}
Expand Down Expand Up @@ -1449,6 +1450,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismrnmi1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismrnmi1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfa -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
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1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -129,6 +129,7 @@ on support follow.
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smepmp`` Supported
``Smrnmi`` Assembly Support
``Smstateen`` Assembly Support
``Ssaia`` Supported
``Ssccfg`` Supported
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -931,6 +931,13 @@ def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0,
"'Smepmp' (Enhanced Physical Memory Protection)">;

def FeatureStdExtSmrnmi
: RISCVExtension<"smrnmi", 1, 0,
"'Smrnmi' (Resumable Non-Maskable Interrupts)">;
def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">,
AssemblerPredicate<(all_of FeatureStdExtSmrnmi),
"'Smrnmi' (Resumable Non-Maskable Interrupts)">;

def FeatureStdExtSmcdeleg
: RISCVExtension<"smcdeleg", 1, 0,
"'Smcdeleg' (Counter Delegation Machine Level)">;
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -815,6 +815,14 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
}
} // isBarrier = 1, isReturn = 1, isTerminator = 1

let Predicates = [HasStdExtSmrnmi] in {
def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
let rd = 0;
let rs1 = 0;
let rs2 = 0b00010;
}
}// Predicates = [HasStdExtSmrnmi]

def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
let rd = 0;
let rs1 = 0;
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -118,6 +118,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
Expand Down Expand Up @@ -261,6 +262,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
Expand Down Expand Up @@ -410,6 +412,7 @@
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
Expand Down Expand Up @@ -551,6 +554,7 @@
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
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3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -327,6 +327,9 @@
.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"

.attribute arch, "rv32i_smrnmi1p0"
# CHECK: attribute 5, "rv32i2p1_smrnmi1p0"

.attribute arch, "rv32i_ssccfg1p0"
# CHECK: attribute 5, "rv32i2p1_ssccfg1p0"

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60 changes: 60 additions & 0 deletions llvm/test/MC/RISCV/machine-csr-names.s
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Expand Up @@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
csrrs t2, 0xB1F, zero


######################################
# Machine Counter Setup
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Section title is incorrect.

The registers are already tested in rv32-machine-csr-names.s but they should be in this file. That was a mistake.

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Okay, I haven't made any modifications to the content of this file

######################################
# mnscratch
# name
# CHECK-INST: csrrs t1, mnscratch, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74]
# CHECK-INST-ALIAS: csrr t1, mnscratch
# uimm12
# CHECK-INST: csrrs t2, mnscratch, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74]
# CHECK-INST-ALIAS: csrr t2, mnscratch
# name
csrrs t1, mnscratch, zero
# uimm12
csrrs t2, 0x740, zero

# mnepc
# name
# CHECK-INST: csrrs t1, mnepc, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74]
# CHECK-INST-ALIAS: csrr t1, mnepc
# uimm12
# CHECK-INST: csrrs t2, mnepc, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74]
# CHECK-INST-ALIAS: csrr t2, mnepc
# name
csrrs t1, mnepc, zero
# uimm12
csrrs t2, 0x741, zero

# mncause
# name
# CHECK-INST: csrrs t1, mncause, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74]
# CHECK-INST-ALIAS: csrr t1, mncause
# uimm12
# CHECK-INST: csrrs t2, mncause, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74]
# CHECK-INST-ALIAS: csrr t2, mncause
# name
csrrs t1, mncause, zero
# uimm12
csrrs t2, 0x742, zero

# mnstatus
# name
# CHECK-INST: csrrs t1, mnstatus, zero
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74]
# CHECK-INST-ALIAS: csrr t1, mnstatus
# uimm12
# CHECK-INST: csrrs t2, mnstatus, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74]
# CHECK-INST-ALIAS: csrr t2, mnstatus
# name
csrrs t1, mnstatus, zero
# uimm12
csrrs t2, 0x744, zero


######################################
# Machine Counter Setup
######################################
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4 changes: 4 additions & 0 deletions llvm/test/MC/RISCV/smrnmi-invalid.s
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@@ -0,0 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+smrnmi < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple riscv64 -mattr=+smrnmi < %s 2>&1 | FileCheck %s

mnret 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
14 changes: 14 additions & 0 deletions llvm/test/MC/RISCV/smrnmi-valid.s
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@@ -0,0 +1,14 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+smrnmi -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+smrnmi -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+smrnmi < %s \
# RUN: | llvm-objdump --mattr=+smrnmi -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+smrnmi < %s \
# RUN: | llvm-objdump --mattr=+smrnmi -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s

# CHECK-INST: mnret
# CHECK: encoding: [0x73,0x00,0x20,0x70]
mnret
1 change: 1 addition & 0 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1065,6 +1065,7 @@ R"(All available -march extensions for RISC-V
smcdeleg 1.0
smcsrind 1.0
smepmp 1.0
smrnmi 1.0
smstateen 1.0
ssaia 1.0
ssccfg 1.0
Expand Down