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[RISCV] Add more instructions for the short forward branch optimizati…
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…on. (#66789)

This adds the shifts and the immediate forms of the instructions that
were already supported.

There are still more instructions that can be predicated, but this is
the rest of what we had in our downstream.
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@topperc
topperc authored Sep 19, 2023
1 parent e145bc4 commit bbe3ee0
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Showing 4 changed files with 554 additions and 4 deletions.
34 changes: 34 additions & 0 deletions llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,23 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
case RISCV::PseudoCCXOR:
case RISCV::PseudoCCADDW:
case RISCV::PseudoCCSUBW:
case RISCV::PseudoCCSLL:
case RISCV::PseudoCCSRL:
case RISCV::PseudoCCSRA:
case RISCV::PseudoCCADDI:
case RISCV::PseudoCCSLLI:
case RISCV::PseudoCCSRLI:
case RISCV::PseudoCCSRAI:
case RISCV::PseudoCCANDI:
case RISCV::PseudoCCORI:
case RISCV::PseudoCCXORI:
case RISCV::PseudoCCSLLW:
case RISCV::PseudoCCSRLW:
case RISCV::PseudoCCSRAW:
case RISCV::PseudoCCADDIW:
case RISCV::PseudoCCSLLIW:
case RISCV::PseudoCCSRLIW:
case RISCV::PseudoCCSRAIW:
return expandCCOp(MBB, MBBI, NextMBBI);
case RISCV::PseudoVSETVLI:
case RISCV::PseudoVSETVLIX0:
Expand Down Expand Up @@ -188,11 +205,28 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
llvm_unreachable("Unexpected opcode!");
case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
}
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
.add(MI.getOperand(5))
Expand Down
23 changes: 23 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1106,12 +1106,31 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
switch (Opcode) {
case RISCV::ADD: return RISCV::PseudoCCADD; break;
case RISCV::SUB: return RISCV::PseudoCCSUB; break;
case RISCV::SLL: return RISCV::PseudoCCSLL; break;
case RISCV::SRL: return RISCV::PseudoCCSRL; break;
case RISCV::SRA: return RISCV::PseudoCCSRA; break;
case RISCV::AND: return RISCV::PseudoCCAND; break;
case RISCV::OR: return RISCV::PseudoCCOR; break;
case RISCV::XOR: return RISCV::PseudoCCXOR; break;

case RISCV::ADDI: return RISCV::PseudoCCADDI; break;
case RISCV::SLLI: return RISCV::PseudoCCSLLI; break;
case RISCV::SRLI: return RISCV::PseudoCCSRLI; break;
case RISCV::SRAI: return RISCV::PseudoCCSRAI; break;
case RISCV::ANDI: return RISCV::PseudoCCANDI; break;
case RISCV::ORI: return RISCV::PseudoCCORI; break;
case RISCV::XORI: return RISCV::PseudoCCXORI; break;

case RISCV::ADDW: return RISCV::PseudoCCADDW; break;
case RISCV::SUBW: return RISCV::PseudoCCSUBW; break;
case RISCV::SLLW: return RISCV::PseudoCCSLLW; break;
case RISCV::SRLW: return RISCV::PseudoCCSRLW; break;
case RISCV::SRAW: return RISCV::PseudoCCSRAW; break;

case RISCV::ADDIW: return RISCV::PseudoCCADDIW; break;
case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break;
case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break;
case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break;
}

return RISCV::INSTRUCTION_LIST_END;
Expand All @@ -1132,6 +1151,10 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
// Check if MI can be predicated and folded into the CCMOV.
if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
return nullptr;
// Don't predicate li idiom.
if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
MI->getOperand(1).getReg() == RISCV::X0)
return nullptr;
// Check if MI has any other defs or physreg uses.
for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) {
// Reject frame index operands, PEI can't handle the predicated pseudos.
Expand Down
87 changes: 87 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1438,6 +1438,21 @@ def PseudoCCSUB : Pseudo<(outs GPR:$dst),
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
def PseudoCCSLL : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU, ReadSFBALU]>;
def PseudoCCSRL : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU, ReadSFBALU]>;
def PseudoCCSRA : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU, ReadSFBALU]>;
def PseudoCCAND : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Expand All @@ -1454,6 +1469,42 @@ def PseudoCCXOR : Pseudo<(outs GPR:$dst),
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;

def PseudoCCADDI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCANDI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCORI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCXORI : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;

// RV64I instructions
def PseudoCCADDW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
Expand All @@ -1465,6 +1516,42 @@ def PseudoCCSUBW : Pseudo<(outs GPR:$dst),
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
def PseudoCCSLLW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU, ReadSFBALU]>;
def PseudoCCSRLW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU, ReadSFBALU]>;
def PseudoCCSRAW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU, ReadSFBALU]>;

def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
ReadSFBALU]>;
}

multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {
Expand Down
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