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Fixing/silencing some warnings that have crept in over time. (#16072)
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benvanik authored Jan 8, 2024
1 parent 776789e commit b55ba25
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Showing 6 changed files with 21 additions and 28 deletions.
9 changes: 8 additions & 1 deletion build_tools/cmake/iree_copts.cmake
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Expand Up @@ -115,6 +115,13 @@ iree_select_compiler_opts(IREE_DEFAULT_COPTS
# https://docs.microsoft.com/en-us/cpp/c-runtime-library/secure-template-overloads
"/D_CRT_SECURE_CPP_OVERLOAD_STANDARD_NAMES"

# MLIR defines std::complex<APFloat>, which is invalid per the C++ spec
# stating that std::complex must only be used with builtin compiler types.
# Until MLIR cleans this up we silence it so that we don't end up with
# a warning per file that includes mlir/IR/BuiltinAttributes.h.
# Tracking issue: https://github.com/llvm/llvm-project/issues/65255
"/D_SILENCE_NONFLOATING_COMPLEX_DEPRECATION_WARNING"

# Configure RTTI generation.
# - /GR - Enable generation of RTTI (default)
# - /GR- - Disables generation of RTTI
Expand Down Expand Up @@ -285,7 +292,7 @@ iree_select_compiler_opts(IREE_DEFAULT_COPTS
# TODO(benvanik): confirm these are all still required and document:
"/wd4146" # operator applied to unsigned type, result still unsigned
"/wd4244" # possible loss of data
"/wd4267" # initializing: possible loss of data
"/wd4267" # initializing: possible loss of data
"/wd5105" # allow: macro expansion producing 'defined' has undefined behavior
)

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Expand Up @@ -18,8 +18,8 @@ class Value;
namespace mlir::iree_compiler::gpu {

/// Forward declarations of all supported strategies.
struct BatchMatmulStrategy;
struct MatmulStrategy;
class BatchMatmulStrategy;
class MatmulStrategy;
class PadStrategy;
class SmallReductionStrategy;
class StagedReductionStrategy;
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Expand Up @@ -10,7 +10,6 @@
#include "iree/compiler/Dialect/Flow/IR/FlowOps.h"
#include "mlir/Analysis/SliceAnalysis.h"
#include "mlir/Dialect/Arith/Utils/Utils.h"
#include "mlir/Dialect/Tensor/IR/Tensor.h"
#include "mlir/Dialect/Tensor/Utils/Utils.h"

namespace mlir::iree_compiler::IREE::Flow {
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Expand Up @@ -8,20 +8,8 @@
#define IREE_COMPILER_DIALECT_FLOW_CONVERSION_TENSORTOFLOW_UTILS_H_

#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"

namespace mlir {
class Location;
class LogicalResult;
class OpBuilder;
class OpFoldResult;
class RewriterBase;
class Value;
namespace tensor {
class ExtractSliceOp;
class InsertSliceOp;
} // namespace tensor
} // namespace mlir
#include "mlir/Dialect/Tensor/IR/Tensor.h"
#include "mlir/IR/PatternMatch.h"

namespace mlir::iree_compiler::IREE::Flow {

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9 changes: 4 additions & 5 deletions runtime/src/iree/builtins/ukernel/arch/x86_64/common_x86_64.h
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Expand Up @@ -50,7 +50,7 @@ static inline __m256i iree_uk_avx2_load_8x4xi8_strided(
const iree_uk_int8_t* src, iree_uk_index_t stride) {
__m256i indices = _mm256_mullo_epi32(
_mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7), _mm256_set1_epi32(stride));
return _mm256_i32gather_epi32(src, indices, 1);
return _mm256_i32gather_epi32((const int*)src, indices, 1);
}

static inline __m128i iree_uk_avx2_load_8x2xi8_strided(
Expand Down Expand Up @@ -264,9 +264,8 @@ static inline __m512i iree_uk_avx512_loadu_4x128_from_16x16xi32(
static inline void iree_uk_avx512_storeu_4x128_to_16x16xi32(
iree_uk_int32_t* dst, int i0, int j0, int i1, int j1, int i2, int j2,
int i3, int j3, __m512i vec512) {
return iree_uk_avx512_storeu_4x128(dst + i0 * 16 + j0, dst + i1 * 16 + j1,
dst + i2 * 16 + j2, dst + i3 * 16 + j3,
vec512);
iree_uk_avx512_storeu_4x128(dst + i0 * 16 + j0, dst + i1 * 16 + j1,
dst + i2 * 16 + j2, dst + i3 * 16 + j3, vec512);
}

static inline __m512i iree_uk_avx512_load_16x4xi8_strided(
Expand Down Expand Up @@ -410,4 +409,4 @@ iree_uk_avx512_copy_16x16xi8_tiled_1x2_transpose_strided_to_strided(

#endif // defined(__AVX2__)

#endif // IREE_BUILTINS_UKERNEL_ARCH_X86_64_COMMON_X86_64_H_
#endif // IREE_BUILTINS_UKERNEL_ARCH_X86_64_COMMON_X86_64_H_
10 changes: 5 additions & 5 deletions runtime/src/iree/vm/ops.h
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Expand Up @@ -14,15 +14,15 @@
#include "iree/base/internal/math.h"
#include "iree/vm/value.h"

// The kernels below has undefined behavior in cases where the corresponding
// The kernels below have undefined behavior in cases where the corresponding
// higher-level ops that map to them have undefined/implementation defined
// behavior and no additional checking was inserted as part of lowering.
// Avoiding UB is expected to happen above this level.
// Note: Setting this variable merely doesn't disable UBSAN.
#if !IREE_VM_UBSAN_CHECKABLE_ENABLE
#if defined(IREE_COMPILER_CLANG) && !IREE_VM_UBSAN_CHECKABLE_ENABLE
#pragma clang attribute push(__attribute__((no_sanitize("undefined"))), \
apply_to = function)
#endif
#endif // IREE_COMPILER_CLANG && !IREE_VM_UBSAN_CHECKABLE_ENABLE

static inline int32_t vm_ext_i8i32u(int32_t);
static inline int32_t vm_ext_i8i32s(int32_t);
Expand Down Expand Up @@ -651,8 +651,8 @@ static inline int32_t vm_cmp_nan_f32(float operand) {
return isnan(operand) ? 1 : 0;
}

#if !IREE_VM_UBSAN_CHECKABLE_ENABLE
#if defined(IREE_COMPILER_CLANG) && !IREE_VM_UBSAN_CHECKABLE_ENABLE
#pragma clang attribute pop
#endif
#endif // IREE_COMPILER_CLANG && !IREE_VM_UBSAN_CHECKABLE_ENABLE

#endif // IREE_VM_OPS_H_

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