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Add a private key provider to accelerate RSA and ECDSA crypto operations on recent Intel Xeon processors. #15871
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For testing is there any way we can run these tests in CI? Not sure how much control we have over processor types in CI. @lizan do you have thoughts on our options here? @envoyproxy/dependency-shepherds for thoughts on adding the dependency. |
If the dep is only uses by the extension I think it's OK with me, but will see if @htuch or @moderation have any concerns. In terms of testing, we have other tests that check for hardware/OS compat before running, though it might be good to also mock to make sure we have good coverage as I'm not sure of CI status and it might change over time. |
We don't have Xeon processor based CI runner today, but we can provision a few to the CI cluster. |
Is the proposed dependency open-source? I couldn't see a link to a repo on the link provided and a "Get Access" button indicating the code is behind a wall. Would be interesting to run the ipp-crypto dependency through the dependency policy at https://github.com/envoyproxy/envoy/blob/main/DEPENDENCY_POLICY.md |
@moderation Here's the repo of the library https://github.com/intel/ipp-crypto |
Thanks for the comments. It seems that writing a mock library for testing the multi-buffer operations using just regular crypto functions would be a good idea. I'll show the DEPENDENCY_POLICY.md list to the ipp-crypto team to get comments to the items there. |
@ipuustin I'd definitely suggest adding a SECURITY.md and plan around how to handle security incidents for something this foundational to transport sec. |
This issue has been automatically marked as stale because it has not had activity in the last 30 days. It will be closed in the next 7 days unless it is tagged "help wanted" or "no stalebot" or other activity occurs. Thank you for your contributions. |
This issue has been automatically closed because it has not had activity in the last 37 days. If this issue is still valid, please ping a maintainer and ask them to label it as "help wanted" or "no stalebot". Thank you for your contributions. |
Intel's IPP (Integrated Performance Primitives) crypto library has support for multi-buffer crypto operations. Briefly, multi-buffer cryptography is implemented with AVX-512 instructions using a SIMD (single instruction, multiple data) mechanism. Up to eight RSA or ECDSA operations are gathered together into a buffer and processed at the same time, providing potentially improved performance. The AVX-512 instructions are available on recently launched 3rd generation Xeon Scalable server processors (Ice Lake server) processors. This commit adds a private key provider to accelerate RSA and ECDSA crypto operations on recent Intel Xeon processors. Every worker thread has a queue of up-to-eight crypto operations. When the queue is full or when the timer is triggered, the queue is processed and all the pending handshakes are notified. The potential performance benefit depends on many factors: the size of the cpuset Envoy is running on, incoming traffic pattern, encryption type (RSA or ECDSA), and key size. In my own testing I saw the biggest performance increase when long RSA keys were used on an Envoy running in a fairly limited environment serving lots of new incoming TLS requests. For more details, see this Intel whitepaper which contains some more information about the AVX-512 instructions and potential performance increase: https://www.intel.com/content/www/us/en/architecture-and-technology/crypto-acceleration-in-xeon-scalable-processors-wp.html Additional Description: One new dependency is introduced: Intel’s ipp-crypto library. Currently the PR is using a development version of ipp-crypto because BoringSSL support is not yet part of any release. The ipp-crypto team has indicated that BoringSSL version will be included in future ipp-crypto releases. Basic tests are provided, and a fake library interface is included for testing on systems without the required AVX-512 instruction set. Risk Level: Medium (TLS security feature, not enabled by default) Testing: Unit tests Docs Changes: API interface is documented Release Notes: Added CryptoMB private key provider to contrib. Platform Specific Features: Requires Intel 3rd generation Xeon Scalable server processor for the AVX-512 IFMA instruction set. Fixes: #15871 Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com> Co-authored-by: Greg Greenway <ggreenway@apple.com>
Intel's IPP (Integrated Performance Primitives) crypto library has support for multi-buffer crypto operations. Briefly, multi-buffer cryptography is implemented with AVX-512 instructions using a SIMD (single instruction, multiple data) mechanism. Up to eight RSA or ECDSA operations are gathered together into a buffer and processed at the same time, providing potentially improved performance. The AVX-512 instructions are available on recently launched 3rd generation Xeon Scalable server processors (Ice Lake server) processors. This commit adds a private key provider to accelerate RSA and ECDSA crypto operations on recent Intel Xeon processors. Every worker thread has a queue of up-to-eight crypto operations. When the queue is full or when the timer is triggered, the queue is processed and all the pending handshakes are notified. The potential performance benefit depends on many factors: the size of the cpuset Envoy is running on, incoming traffic pattern, encryption type (RSA or ECDSA), and key size. In my own testing I saw the biggest performance increase when long RSA keys were used on an Envoy running in a fairly limited environment serving lots of new incoming TLS requests. For more details, see this Intel whitepaper which contains some more information about the AVX-512 instructions and potential performance increase: https://www.intel.com/content/www/us/en/architecture-and-technology/crypto-acceleration-in-xeon-scalable-processors-wp.html Additional Description: One new dependency is introduced: Intel’s ipp-crypto library. Currently the PR is using a development version of ipp-crypto because BoringSSL support is not yet part of any release. The ipp-crypto team has indicated that BoringSSL version will be included in future ipp-crypto releases. Basic tests are provided, and a fake library interface is included for testing on systems without the required AVX-512 instruction set. Risk Level: Medium (TLS security feature, not enabled by default) Testing: Unit tests Docs Changes: API interface is documented Release Notes: Added CryptoMB private key provider to contrib. Platform Specific Features: Requires Intel 3rd generation Xeon Scalable server processor for the AVX-512 IFMA instruction set. Fixes: envoyproxy#15871 Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com> Co-authored-by: Greg Greenway <ggreenway@apple.com>
Title: Add a private key provider to accelerate RSA and ECDSA crypto operations on recent Intel Xeon processors.
Description:
Intel's IPP (Integrated Performance Primitives) crypto library has support for multi-buffer crypto operations. Briefly, multi-buffer cryptography is implemented with AVX-512 instructions using a SIMD (single instruction, multiple data) mechanism. Up to eight RSA or ECDSA operations are gathered together into a buffer and processed with a single instruction, providing potentially improved performance. The AVX-512 instructions are available on recently launched Intel Ice Lake Server processors.
We have an Envoy private key provider in the works which we would like to submit as a PR soon. There are a few opens which we would like to get feedback on:
Relevant Links:
https://en.wikipedia.org/wiki/Integrated_Performance_Primitives
https://software.intel.com/content/www/us/en/develop/tools/oneapi/components/ipp.html
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