Merge pull request #535 from antmicro/arty-cv32e40p

Add support for the CV32E40P RISC-V CPU
enjoy-digital · May 22, 2020 · 4c4cd33 · 4c4cd33
2 parents 7d09ea1 + 2d6ee5a
commit 4c4cd33
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diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
@@ -57,6 +57,7 @@ class CPUNone(CPU):
 from litex.soc.cores.cpu.vexriscv import VexRiscv
 from litex.soc.cores.cpu.rocket import RocketRV64
 from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
+from litex.soc.cores.cpu.cv32e40p import CV32E40P
 
 CPUS = {
     # None
@@ -76,6 +77,7 @@ class CPUNone(CPU):
     "picorv32"    : PicoRV32,
     "minerva"     : Minerva,
     "vexriscv"    : VexRiscv,
+    "cv32e40p"    : CV32E40P,
 
     # RISC-V 64-bit
     "rocket"      : RocketRV64,

diff --git a/litex/soc/cores/cpu/cv32e40p/__init__.py b/litex/soc/cores/cpu/cv32e40p/__init__.py
@@ -0,0 +1 @@
+from litex.soc.cores.cpu.cv32e40p.core import CV32E40P
diff --git a/litex/soc/cores/cpu/cv32e40p/boot-helper.S b/litex/soc/cores/cpu/cv32e40p/boot-helper.S
@@ -0,0 +1,4 @@
+.section    .text, "ax", @progbits
+.global     boot_helper
+boot_helper:
+	jr x13
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		from litex.soc.cores.cpu.cv32e40p.core import CV32E40P