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Optimize "(vec & cns) == zero" on arm64 #102705

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Optimize "(vec & cns) == zero" on arm64 #102705

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c90e724
Optimize "(vec & cns) == zero" on arm64
EgorBo May 26, 2024
eb6ccee
improve codegen
EgorBo May 26, 2024
26d908c
fix build
EgorBo May 27, 2024
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39 changes: 36 additions & 3 deletions src/coreclr/jit/lowerarmarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1460,17 +1460,37 @@ GenTree* Lowering::LowerHWIntrinsicCmpOp(GenTreeHWIntrinsic* node, genTreeOps cm
// Special case: "vec ==/!= zero_vector"
if (!varTypeIsFloating(simdBaseType) && (op != nullptr) && (simdSize != 12))
{
GenTree* cmp = op;
uint64_t scalarAndMask = UINT64_MAX;
GenTree* cmp = op;
if (simdSize != 8) // we don't need compression for Vector64
{
CorInfoType pairwiseMaxType = CORINFO_TYPE_UINT;

// If op is "vec & cnsVec" where both u64 components in that cnsVec are the same (for both SIMD12 and
// SIMD16) then we'd better do this AND on top of TYP_LONG NI_AdvSimd_Extract in the end - it produces a
// more optimal codegen.
if (op->OperIsHWIntrinsic(NI_AdvSimd_And) && op->AsHWIntrinsic()->Op(2)->OperIs(GT_CNS_VEC))
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This doesn't have to be a constant right?

Just any (x & y) == zero or (x & y) != zero can be optimzied down to a tst (on both xarch and arm64).

{
GenTreeVecCon* andMask = op->AsHWIntrinsic()->Op(2)->AsVecCon();
simd16_t val = andMask->gtSimd16Val;
if (ElementsAreSame(val.i8, 16) && emitter::emitIns_valid_imm_for_alu(val.i64[0], EA_8BYTE))
{
pairwiseMaxType = CORINFO_TYPE_UBYTE;
scalarAndMask = val.u64[0];
BlockRange().Remove(op);
BlockRange().Remove(andMask);
op = op->AsHWIntrinsic()->Op(1);
}
}

node->Op(1) = op;
LIR::Use tmp1Use(BlockRange(), &node->Op(1), node);
ReplaceWithLclVar(tmp1Use);
op = node->Op(1);
GenTree* opClone = comp->gtClone(op);
BlockRange().InsertAfter(op, opClone);

cmp = comp->gtNewSimdHWIntrinsicNode(simdType, op, opClone, NI_AdvSimd_Arm64_MaxPairwise, CORINFO_TYPE_UINT,
cmp = comp->gtNewSimdHWIntrinsicNode(simdType, op, opClone, NI_AdvSimd_Arm64_MaxPairwise, pairwiseMaxType,
simdSize);
BlockRange().InsertBefore(node, cmp);
LowerNode(cmp);
Expand All @@ -1483,7 +1503,20 @@ GenTree* Lowering::LowerHWIntrinsicCmpOp(GenTreeHWIntrinsic* node, genTreeOps cm

GenTree* val =
comp->gtNewSimdHWIntrinsicNode(TYP_LONG, cmp, zroCns, NI_AdvSimd_Extract, CORINFO_TYPE_ULONG, simdSize);
BlockRange().InsertAfter(zroCns, val);

// Apply the scalar AND mask
if (scalarAndMask != UINT64_MAX)
{
GenTree* andMaskNode = comp->gtNewIconNode(static_cast<ssize_t>(scalarAndMask), TYP_LONG);
GenTree* andNode = comp->gtNewOperNode(GT_AND, TYP_LONG, val, andMaskNode);
BlockRange().InsertAfter(zroCns, val, andMaskNode, andNode);
LowerNode(val);
val = andNode;
}
else
{
BlockRange().InsertAfter(zroCns, val);
}
LowerNode(val);

GenTree* cmpZeroCns = comp->gtNewIconNode(0, TYP_LONG);
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