Verilua is a versatile simulation framework for Hardware Verification based on LuaJIT. It can be used as a Hardwave Verification Language (HVL) to write testbenches and simulate hardware designs. Or it can be used as a Hardware Script Engine (HSE) to embed Lua scripts into the simulation. It can also can be used as a Waveform Analysis Language(WAL) to analyze the provided waveform files(VCD, FST, FSDB, etc).
Please refer to the documentation for more information.