systemverilog: add dedicated wildcard operator errors

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
chipsalliance · Apr 22, 2022 · 8683b30 · 8683b30
1 parent 55c26d7
commit 8683b30
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
@@ -2437,6 +2437,13 @@ void UhdmAst::process_operation()
     case vpiAssignmentPatternOp:
         process_assignment_pattern_op();
         break;
+    case vpiWildEqOp:
+    case vpiWildNeqOp: {
+        const uhdm_handle *const handle = (const uhdm_handle *)obj_h;
+        const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
+        report_error("%s:%d: Wildcard operators are not supported yet\n", object->VpiFile().c_str(), object->VpiLineNo());
+        break;
+    }
     default: {
         current_node = make_ast_node(AST::AST_NONE);
         visit_one_to_many({vpiOperand}, obj_h, [&](AST::AstNode *node) {