Workaround Chisel 3.4 naming bug

chipsalliance · Oct 14, 2020 · f05f772 · f05f772
1 parent 5c0c935
commit f05f772
Showing 1 changed file with 4 additions and 3 deletions.
diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.devices.debug
 
 import chisel3._
-import chisel3.experimental.IntParam
+import chisel3.experimental.{IntParam, noPrefix}
 import chisel3.util._
 import chisel3.util.HasBlackBoxResource
 import freechips.rocketchip.config.{Field, Parameters}
@@ -109,7 +109,8 @@ trait HasPeripheryDebugModuleImp extends LazyModuleImp {
     resetctrl
   }
 
-  val debug = outer.debugOpt.map { outerdebug =>
+  // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603
+  val debug = noPrefix(outer.debugOpt.map { outerdebug =>
     val debug = IO(new DebugIO)
 
     require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined),
@@ -145,7 +146,7 @@ trait HasPeripheryDebugModuleImp extends LazyModuleImp {
     outerdebug.module.io.ctrl.debugUnavail.foreach { _ := false.B }
 
     debug
-  }
+  })
 
   val dtm = debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_)))