Update RVV whole-register load/store opcodes

riscvarchive/riscv-v-spec@20f673c
chipsalliance · Jul 12, 2020 · d1d79c7 · d1d79c7
1 parent 3f03ba8
commit d1d79c7
Showing 1 changed file with 19 additions and 1 deletion.
diff --git a/src/main/scala/rocket/Instructions.scala b/src/main/scala/rocket/Instructions.scala
@@ -351,8 +351,26 @@ object Instructions {
   def VLE16FF_V          = BitPat("b???000?10000?????101?????0000111")
   def VLE32FF_V          = BitPat("b???000?10000?????110?????0000111")
   def VLE64FF_V          = BitPat("b???000?10000?????111?????0000111")
-  def VL1R_V             = BitPat("b000000101000?????000?????0000111")
+  def VL1RE8_V           = BitPat("b000000101000?????000?????0000111")
+  def VL1RE16_V          = BitPat("b000000101000?????101?????0000111")
+  def VL1RE32_V          = BitPat("b000000101000?????110?????0000111")
+  def VL1RE64_V          = BitPat("b000000101000?????111?????0000111")
+  def VL2RE8_V           = BitPat("b001000101000?????000?????0000111")
+  def VL2RE16_V          = BitPat("b001000101000?????101?????0000111")
+  def VL2RE32_V          = BitPat("b001000101000?????110?????0000111")
+  def VL2RE64_V          = BitPat("b001000101000?????111?????0000111")
+  def VL4RE8_V           = BitPat("b011000101000?????000?????0000111")
+  def VL4RE16_V          = BitPat("b011000101000?????101?????0000111")
+  def VL4RE32_V          = BitPat("b011000101000?????110?????0000111")
+  def VL4RE64_V          = BitPat("b011000101000?????111?????0000111")
+  def VL8RE8_V           = BitPat("b111000101000?????000?????0000111")
+  def VL8RE16_V          = BitPat("b111000101000?????101?????0000111")
+  def VL8RE32_V          = BitPat("b111000101000?????110?????0000111")
+  def VL8RE64_V          = BitPat("b111000101000?????111?????0000111")
   def VS1R_V             = BitPat("b000000101000?????000?????0100111")
+  def VS2R_V             = BitPat("b001000101000?????000?????0100111")
+  def VS4R_V             = BitPat("b011000101000?????000?????0100111")
+  def VS8R_V             = BitPat("b111000101000?????000?????0100111")
   def VFADD_VF           = BitPat("b000000???????????101?????1010111")
   def VFSUB_VF           = BitPat("b000010???????????101?????1010111")
   def VFMIN_VF           = BitPat("b000100???????????101?????1010111")