AXI4: add CreditedIO unit tests

chipsalliance · Jul 15, 2020 · 30a410f · 30a410f
1 parent 5851fc3
commit 30a410f
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Showing 2 changed files with 31 additions and 1 deletion.
diff --git a/src/main/scala/amba/axi4/Credited.scala b/src/main/scala/amba/axi4/Credited.scala
@@ -82,3 +82,32 @@ object AXI4CreditedSink {
   def apply(delay: CreditedDelay)(implicit p: Parameters): AXI4CreditedSinkNode = apply(AXI4CreditedDelay(delay))
   def apply()(implicit p: Parameters): AXI4CreditedSinkNode = apply(CreditedDelay(1, 1))
 }
+
+/** Synthesizeable unit tests */
+import freechips.rocketchip.unittest._
+
+class AXI4RAMCreditedCrossing(txns: Int, params: CreditedCrossing)(implicit p: Parameters) extends LazyModule {
+  val model = LazyModule(new TLRAMModel("AXI4CreditedCrossing"))
+  val fuzz = LazyModule(new TLFuzzer(txns))
+  val toaxi = LazyModule(new TLToAXI4)
+  val island = LazyModule(new CrossingWrapper(params))
+  val ram  = island { LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) }
+
+  island.crossAXI4In(ram.node) := toaxi.node := TLDelayer(0.1) := model.node := fuzz.node
+
+  lazy val module = new LazyModuleImp(this) with UnitTestModule {
+    io.finished := fuzz.module.io.finished
+  }
+}
+
+class AXI4RAMCreditedCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut_1000 = Module(LazyModule(new AXI4RAMCreditedCrossing(txns, CreditedCrossing(CreditedDelay(1, 0), CreditedDelay(0, 0)))).module)
+  val dut_0100 = Module(LazyModule(new AXI4RAMCreditedCrossing(txns, CreditedCrossing(CreditedDelay(0, 1), CreditedDelay(0, 0)))).module)
+  val dut_0010 = Module(LazyModule(new AXI4RAMCreditedCrossing(txns, CreditedCrossing(CreditedDelay(0, 0), CreditedDelay(1, 0)))).module)
+  val dut_0001 = Module(LazyModule(new AXI4RAMCreditedCrossing(txns, CreditedCrossing(CreditedDelay(0, 0), CreditedDelay(0, 1)))).module)
+  val dut_1111 = Module(LazyModule(new AXI4RAMCreditedCrossing(txns, CreditedCrossing(CreditedDelay(1, 1), CreditedDelay(1, 1)))).module)
+
+  val duts = Seq(dut_1000, dut_0100, dut_0010, dut_0001, dut_1111)
+  duts.foreach { _.io.start := true.B }
+  io.finished := duts.map(_.io.finished).reduce(_ && _)
+}
diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala
@@ -34,7 +34,8 @@ class WithAMBAUnitTests extends Config((site, here, up) => {
       Module(new AXI4FullFuzzRAMTest(        txns=3*txns, timeout=timeout)),
       Module(new AXI4BridgeTest(             txns=3*txns, timeout=timeout)),
       Module(new AXI4XbarTest(               txns=1*txns, timeout=timeout)),
-      Module(new AXI4RAMAsyncCrossingTest(   txns=3*txns, timeout=timeout))) }
+      Module(new AXI4RAMAsyncCrossingTest(   txns=3*txns, timeout=timeout)),
+      Module(new AXI4RAMCreditedCrossingTest(txns=3*txns, timeout=timeout))) }
 })
 
 class WithTLSimpleUnitTests extends Config((site, here, up) => {