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making updates to enable verilator compilation
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Michael Norris committed Oct 22, 2024
1 parent 6929276 commit 71546ba
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Showing 6 changed files with 80 additions and 39 deletions.
67 changes: 45 additions & 22 deletions src/abr_libs/rtl/abr_piso.sv
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Expand Up @@ -12,47 +12,71 @@
// See the License for the specific language governing permissions and
// limitations under the License.

// PISO supports 4 modes of operation, each with unique input and output rates

module abr_piso
// import ::*;
#(
parameter PISO_NUM_MODE = 1
,parameter PISO_BUFFER_W = 1344
,parameter integer PISO_INPUT_RATE[PISO_NUM_MODE-1:0] = {1088}
,parameter integer PISO_OUTPUT_RATE[PISO_NUM_MODE-1:0] = {80}
#( parameter PISO_BUFFER_W = 1344
,parameter PISO_PTR_W = $clog2(PISO_BUFFER_W)
,parameter PISO_INPUT_RATE0 = 1088
,parameter PISO_INPUT_RATE1 = 1088
,parameter PISO_INPUT_RATE2 = 1088
,parameter PISO_INPUT_RATE3 = 1088
,parameter PISO_OUTPUT_RATE0 = 80
,parameter PISO_OUTPUT_RATE1 = 80
,parameter PISO_OUTPUT_RATE2 = 80
,parameter PISO_OUTPUT_RATE3 = 80
,parameter PISO_ACT_INPUT_RATE = 1088
,parameter PISO_ACT_OUTPUT_RATE = 80
)
(
input logic clk,
input logic rst_b,
input logic zeroize,

//input data
input logic [$clog2(PISO_NUM_MODE)-1:0] mode,
input logic [1:0] mode,
input logic valid_i,
output logic hold_o,
input logic [PISO_INPUT_RATE[0]-1:0] data_i,
input logic [PISO_ACT_INPUT_RATE-1:0] data_i,

//Output data
output logic valid_o,
input logic hold_i,
output logic [PISO_OUTPUT_RATE[0]-1:0] data_o
output logic [PISO_ACT_OUTPUT_RATE-1:0] data_o

);

parameter PISO_PTR_W = $clog2(PISO_BUFFER_W);
parameter BUFFER_W_DELTA = PISO_BUFFER_W - PISO_INPUT_RATE[0];
parameter PISO_NUM_MODE = 4;
parameter BUFFER_W_DELTA = PISO_BUFFER_W - PISO_ACT_INPUT_RATE;

logic [PISO_BUFFER_W-1:0] buffer, buffer_d;
logic [PISO_PTR_W-1:0] buffer_wr_ptr, buffer_wr_ptr_d;

logic [PISO_PTR_W-1:0] current_input_rate, current_output_rate;

logic buffer_wr, buffer_rd;
logic update_buffer;

always_comb begin
unique case (mode)
2'b00: current_input_rate = PISO_INPUT_RATE0;
2'b01: current_input_rate = PISO_INPUT_RATE1;
2'b10: current_input_rate = PISO_INPUT_RATE2;
2'b11: current_input_rate = PISO_INPUT_RATE3;
endcase

unique case (mode)
2'b00: current_output_rate = PISO_OUTPUT_RATE0;
2'b01: current_output_rate = PISO_OUTPUT_RATE1;
2'b10: current_output_rate = PISO_OUTPUT_RATE2;
2'b11: current_output_rate = PISO_OUTPUT_RATE3;
endcase
end

//hold when not enough room for full input data
always_comb hold_o = buffer_wr_ptr > (PISO_BUFFER_W[PISO_PTR_W-1:0] - PISO_INPUT_RATE[mode][PISO_PTR_W-1:0]);
always_comb hold_o = buffer_wr_ptr > (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate);

always_comb data_o = buffer[PISO_OUTPUT_RATE[0]-1:0];
always_comb valid_o = buffer_wr_ptr >= PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0];
always_comb data_o = buffer[PISO_ACT_OUTPUT_RATE-1:0];
always_comb valid_o = buffer_wr_ptr >= current_output_rate;

always_comb buffer_wr = valid_i & ~hold_o;
always_comb buffer_rd = valid_o & ~hold_i;
Expand All @@ -76,9 +100,9 @@ module abr_piso
always_comb begin
unique case ({buffer_rd, buffer_wr})
2'b00 : buffer_wr_ptr_d = buffer_wr_ptr;
2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + PISO_INPUT_RATE[mode][PISO_PTR_W-1:0];
2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0];
2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (PISO_INPUT_RATE[mode][PISO_PTR_W-1:0] - PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0]);
2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + current_input_rate;
2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - current_output_rate;
2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (current_input_rate - current_output_rate);
default : buffer_wr_ptr_d = buffer_wr_ptr;
endcase
end
Expand All @@ -91,7 +115,7 @@ module abr_piso
buffer_wdata_mask = '1;
for (int i = 0; i < PISO_NUM_MODE; i++) begin
if (i == mode) begin
buffer_wdata_mask = PISO_BUFFER_W'(buffer_wdata_mask >> (PISO_BUFFER_W[PISO_PTR_W-1:0] - PISO_INPUT_RATE[mode][PISO_PTR_W-1:0]));
buffer_wdata_mask = PISO_BUFFER_W'(buffer_wdata_mask >> (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate));
end
end
buffer_wdata = {{BUFFER_W_DELTA{1'b0}},data_i} & buffer_wdata_mask;
Expand All @@ -101,13 +125,12 @@ module abr_piso
always_comb begin
unique case ({buffer_rd, buffer_wr})
2'b00 : buffer_d = buffer;
2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> PISO_OUTPUT_RATE[mode]);
2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> current_output_rate);
2'b01 : buffer_d = PISO_BUFFER_W'(buffer_wdata << buffer_wr_ptr) | buffer;
2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_wr_ptr - PISO_OUTPUT_RATE[mode][PISO_PTR_W-1:0])) | PISO_BUFFER_W'(buffer >> PISO_OUTPUT_RATE[mode]);
2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_wr_ptr - current_output_rate)) | PISO_BUFFER_W'(buffer >> current_output_rate);

default : buffer_d = buffer;
endcase
end
// {{PISO_BUFFER_W - PISO_INPUT_RATE[mode]{1'b0}},

endmodule
13 changes: 10 additions & 3 deletions src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -380,10 +380,17 @@ always_comb sampler_ntt_data_o = rejs_data;

//one piso
abr_piso #(
.PISO_NUM_MODE(4),
.PISO_BUFFER_W(REJS_PISO_BUFFER_W),
.PISO_INPUT_RATE({SIB_PISO_INPUT_RATE,EXP_PISO_INPUT_RATE,REJB_PISO_INPUT_RATE,REJS_PISO_INPUT_RATE}),
.PISO_OUTPUT_RATE({SIB_PISO_OUTPUT_RATE,EXP_PISO_OUTPUT_RATE,REJB_PISO_OUTPUT_RATE,REJS_PISO_OUTPUT_RATE})
.PISO_INPUT_RATE0(REJS_PISO_INPUT_RATE),
.PISO_INPUT_RATE1(REJB_PISO_INPUT_RATE),
.PISO_INPUT_RATE2(EXP_PISO_INPUT_RATE),
.PISO_INPUT_RATE3(SIB_PISO_INPUT_RATE),
.PISO_OUTPUT_RATE0(REJS_PISO_OUTPUT_RATE),
.PISO_OUTPUT_RATE1(REJB_PISO_OUTPUT_RATE),
.PISO_OUTPUT_RATE2(EXP_PISO_OUTPUT_RATE),
.PISO_OUTPUT_RATE3(SIB_PISO_OUTPUT_RATE),
.PISO_ACT_INPUT_RATE(REJS_PISO_INPUT_RATE),
.PISO_ACT_OUTPUT_RATE(REJS_PISO_OUTPUT_RATE)
) abr_piso_inst (
.clk(clk),
.rst_b(rst_b),
Expand Down
20 changes: 13 additions & 7 deletions src/mldsa_top/rtl/mldsa_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -445,21 +445,27 @@ module mldsa_ctrl
assign mldsa_reg_hwif_in.MLDSA_PRIVKEY_IN.rd_data = '0;


logic privkey_out_rd_ack, signature_rd_ack, pubkey_rd_ack;

always_comb mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_ack = privkey_out_rd_ack;
always_comb mldsa_reg_hwif_in.MLDSA_SIGNATURE.rd_ack = signature_rd_ack;
always_comb mldsa_reg_hwif_in.MLDSA_PUBKEY.rd_ack = pubkey_rd_ack;

//ack the read request one clock later
always_ff @(posedge clk or negedge rst_b) begin
if (!rst_b) begin
mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_ack <= 0;
mldsa_reg_hwif_in.MLDSA_SIGNATURE.rd_ack <= 0;
mldsa_reg_hwif_in.MLDSA_PUBKEY.rd_ack <= 0;
privkey_out_rd_ack <= 0;
signature_rd_ack <= 0;
pubkey_rd_ack <= 0;
end
else begin
mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_ack <= mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & ~mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr;
mldsa_reg_hwif_in.MLDSA_SIGNATURE.rd_ack <= mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & ~mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr;
mldsa_reg_hwif_in.MLDSA_PUBKEY.rd_ack <= mldsa_reg_hwif_out.MLDSA_PUBKEY.req & ~mldsa_reg_hwif_out.MLDSA_PUBKEY.req_is_wr;
privkey_out_rd_ack <= mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & ~mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr;
signature_rd_ack <= mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & ~mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr;
pubkey_rd_ack <= mldsa_reg_hwif_out.MLDSA_PUBKEY.req & ~mldsa_reg_hwif_out.MLDSA_PUBKEY.req_is_wr;
end
end

always_comb mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_data = mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_ack & mldsa_valid_reg & keygen_process ? privkey_out_rdata : 0;
always_comb mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_data = privkey_out_rd_ack & mldsa_valid_reg & keygen_process ? privkey_out_rdata : 0;

//No write to PRIVKEY_OUT allowed - just ack it
assign mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.wr_ack = mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr;
Expand Down
5 changes: 4 additions & 1 deletion src/mldsa_top/rtl/mldsa_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -358,6 +358,9 @@ mldsa_ctrl mldsa_control_inst

);

logic [MsgWidth-1:0] msg_data_i[Sha3Share];
assign msg_data_i = decomp_msg_valid ? decomp_msg_data : msg_data;

mldsa_sampler_top sampler_top_inst
(
.clk(clk),
Expand All @@ -370,7 +373,7 @@ mldsa_sampler_top sampler_top_inst
.msg_valid_i(msg_valid | decomp_msg_valid), //msg interface valid //FIXME
.msg_rdy_o(msg_rdy), //msg interface rdy (~hold)
.msg_strobe_i(decomp_msg_valid ? '1 : msg_strobe), //msg byte enables //FIXME
.msg_data_i(decomp_msg_valid ? decomp_msg_data : msg_data), //msg data/ /FIXME
.msg_data_i(msg_data_i), //msg data/ /FIXME

.sib_mem_rd_req_i(sib_mem_rd_req),
.sib_mem_rd_data_o(sib_mem_rd_data),
Expand Down
4 changes: 3 additions & 1 deletion src/sigdecode_h/rtl/sigdecode_h_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -289,7 +289,9 @@ module sigdecode_h_ctrl
rd_wr_en = RW_WRITE;
rst_bitmap = arc_SDH_WR_MEM_SDH_WR_INIT | arc_SDH_WR_MEM_SDH_WR_IDLE;
end

default: begin

end
endcase
end

Expand Down
10 changes: 5 additions & 5 deletions src/sk_decode/rtl/skdecode_s1s2_unpack.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,11 @@ module skdecode_s1s2_unpack
logic [REG_SIZE-1:0] eta_minus_data;

always_comb begin
data_o = '0;
valid_o = '0;
error_o = '0;
eta_minus_data = '0;

if (enable) begin
error_o = 'b0;
eta_minus_data = REG_SIZE'(MLDSA_ETA - data_i);
Expand All @@ -63,11 +68,6 @@ module skdecode_s1s2_unpack

valid_o = 'b1;
end
else begin
data_o = '0;
valid_o = '0;
error_o = '0;
end
end

endmodule

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